Commit Graph

49 Commits

Author SHA1 Message Date
Florent Kermarrec 2bb9c6b649 add verilog backend to use the core with a "standard" flow 2015-01-19 20:38:48 +01:00
Florent Kermarrec d84ae7c80c clean up 2015-01-19 18:13:43 +01:00
Florent Kermarrec 79dbb6da4b replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows) 2015-01-19 09:45:34 +01:00
Florent Kermarrec 6de7e15a0c refactor code 2015-01-17 13:22:52 +01:00
Florent Kermarrec 6f2c7a236c add support of identify device command 2015-01-17 02:35:25 +01:00
Florent Kermarrec 175618bcb4 use csr_data_width of 32 to speed up data mila upload 2015-01-16 20:57:01 +01:00
Florent Kermarrec 083bd54121 global clean up
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
2015-01-16 20:26:15 +01:00
Florent Kermarrec d13366dd2d bist: use hardware counter for speed calc and remove loops mode 2015-01-16 18:48:34 +01:00
Florent Kermarrec 1170a1070b add need_reset from controller to request system reset when SATA is not locked 2015-01-15 00:56:47 +01:00
Florent Kermarrec 788546c6ae add frontend and improve BIST 2015-01-14 15:47:13 +01:00
Florent Kermarrec 62f55e32cf use new submodules/specials/clock_domains automatic collection 2015-01-12 13:14:26 +01:00
Florent Kermarrec d196a517d6 use 166MHz clock 2015-01-08 22:58:26 +01:00
Florent Kermarrec 4deda89dcb simplify bist 2015-01-07 22:15:57 +01:00
Florent Kermarrec aa8c0c983c add option to implement or not mila (to see real ressource usage of the SATA controller) 2014-12-24 15:57:42 +01:00
Florent Kermarrec 8b1522bbc9 clean up TestDesign 2014-12-24 15:05:17 +01:00
Florent Kermarrec 7df1d75dee use max_count of 16 and clean up 2014-12-23 23:19:48 +01:00
Florent Kermarrec 74dd907503 add test_bist_mila to show how to capture data 2014-12-23 21:00:38 +01:00
Florent Kermarrec 3e5a4ab097 add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock 2014-12-23 20:41:13 +01:00
Florent Kermarrec 678ee33af4 improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
Florent Kermarrec 38d3f3697b test bist at high speed(working) 2014-12-23 01:39:41 +01:00
Florent Kermarrec 46b2d02783 test bist at slow speed (working) 2014-12-23 00:41:39 +01:00
Florent Kermarrec 6b12782816 read/write seems OK with CommandGenerator 2014-12-23 00:08:22 +01:00
Florent Kermarrec 5e513c25c2 link: fix rx path 2014-12-22 20:58:38 +01:00
Florent Kermarrec eebc2abcda add mode generic CommandGenerator for debug 2014-12-20 16:21:26 +01:00
Florent Kermarrec f495639f22 add primitives decoding in test_identify to ease debug 2014-12-20 01:26:58 +01:00
Florent Kermarrec 35050ece9f add fsms to mila for debug 2014-12-20 00:03:03 +01:00
Florent Kermarrec ea2b06b285 fix phy datapath, first communications between SATACON and a HDD... :) 2014-12-19 22:20:41 +01:00
Florent Kermarrec a79696641a prepare identify test with SATACON 2014-12-19 19:05:49 +01:00
Florent Kermarrec 880c7e7ecc test: change UART baudrate and test SATACONTRemover 2014-12-19 17:45:02 +01:00
Florent Kermarrec 9e14b1b051 use new implicit submodules collection and Pipeline 2014-12-19 01:35:18 +01:00
Florent Kermarrec 4f22bc807a make ctrl/datapath in phy vendor agnostics and simplify imports 2014-12-18 19:45:21 +01:00
Florent Kermarrec 0f8f89a269 update clock constraints for SATA1 and use sys_clk of 200MHz
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
Florent Kermarrec 5a16a5b46d add very basic PHY stimulator (to see HDD behaviour when we send primitives) 2014-12-17 17:57:37 +01:00
Florent Kermarrec 2c0115262b fix compilation and use new cpu_csr_regions 2014-12-17 12:03:52 +01:00
Florent Kermarrec 8f9efde39e regroup all constants/ definitions in common 2014-12-14 10:45:26 +01:00
Florent Kermarrec 64ed34b35a clean up 2014-11-11 16:15:28 +01:00
Florent Kermarrec 47b5ff5e33 move code and create a directory for each layer 2014-11-03 17:38:12 +01:00
Florent Kermarrec 3f7406a937 various fixes and simplifications, SATA1 & SATA2 OK 2014-10-28 02:15:19 +01:00
Florent Kermarrec e2cbb3a048 platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows) 2014-10-24 12:32:08 +02:00
Florent Kermarrec b284819d18 revert simulation design and add wave 2014-09-30 11:10:15 +02:00
Florent Kermarrec 110580eb2e add .payload. to Sink and Source to be compatible with upstream Migen 2014-09-30 11:03:36 +02:00
Florent Kermarrec f5001751d0 instanciate GTXE2_COMMON (seems recommended in AR43339) 2014-09-30 10:57:52 +02:00
Florent Kermarrec cf084fd079 test to visualize OOB with Miscope 2014-09-30 10:17:15 +02:00
Florent Kermarrec 0791b9e2e4 sim working 2014-09-29 17:12:02 +02:00
Florent Kermarrec c27f24c4c0 reorganize code
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
Florent Kermarrec 879478a6e4 clocking: clean up and add comments 2014-09-27 13:33:43 +02:00
Florent Kermarrec 1d053bd7ee modify TestDesign to be able to simulate phy with host <--> device loopback 2014-09-25 15:37:49 +02:00
Florent Kermarrec 435bc22fa0 integrate phy in test design and start fix syntax errors 2014-09-24 16:07:34 +02:00
Florent Kermarrec 7e31ef2152 init with repo with simple TestDesign 2014-09-22 13:36:43 +02:00