9fd9eaea07
Move patch script to python-data
2021-06-27 01:31:05 +02:00
ac217d818f
Set environmental variables in python
2021-06-27 01:07:27 +02:00
e3f6d8349b
Use os methods to expand env vars
2021-06-26 16:30:54 +02:00
b787ee4411
Move systemverilog files to python-data
2021-06-26 15:45:48 +02:00
16b3e08c17
Copy config loader in python
2021-06-26 15:37:17 +02:00
23afca3de8
Merge pull request #953 from developandplay/blackparrot-32bit-csr
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Blackparrot 32bit csr
2021-06-23 19:20:51 +02:00
edc4c85615
build/lattice/common: Add ECP5 Differential Output support.
2021-06-23 11:55:22 +02:00
adb71bde8c
Adjust wishbone adapter for 32bits
2021-06-22 23:37:24 +02:00
b795f848a2
Fixup blackparrot
2021-06-22 18:43:17 +02:00
c395a8068a
cores/prbs: Minor Cleanup and make sure to generate errors when RX is Idle.
2021-06-22 16:57:00 +02:00
2cd6224acf
clock/lattice_ecp5/ECP5PLL: Add expose_dpa method (Dynamic Phase Adjustment) and move code to it.
2021-06-22 12:07:39 +02:00
09a3ca6fd0
Merge pull request #949 from zyp/ecp5_dynamic_pll
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cores/clock/ecp5: Add dynamic phase adjustment signals.
2021-06-22 12:04:20 +02:00
26df3fa2c4
Merge pull request #952 from smunaut/dfu
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build/DFUProg: Allow to specify alt interface and to not reboot
2021-06-22 12:03:43 +02:00
3d81c9a437
build/lattice/LatticeProgrammer: pgrcmd always seems to return a non-zero value so disable check.
2021-06-22 11:59:42 +02:00
f381cdcd1a
build/GenericProgrammer: Add check parameter to make check optional.
2021-06-22 11:59:38 +02:00
38e46bb3d3
build/DFUProg: Allow to specify alt interface and to not reboot
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Some targets have multiple alt settings for DFU for different zone
of the flash. Allowing to specify which one to flash and not
rebooting immediately allows to flash several of them at once.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-06-21 16:12:55 +02:00
d6f24f2f68
cores/uart/RS232ClkPhaseAccum: Avoid reset on phase signal, improve timings/resources on iCE40.
2021-06-20 14:33:25 +02:00
4c8184fbb6
cores/uart: Fix refactoring typo (tick is a 1-bit Signal), thanks @tnt.
2021-06-20 08:58:45 +02:00
b58c416a24
cores/clock/ecp5: Add dynamic phase adjustment signals.
2021-06-19 11:24:08 +02:00
e7d04a2d1b
Merge pull request #948 from developandplay/non-interactive
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Expose non-interactive mode
2021-06-18 13:27:18 +02:00
7d2e19ac26
Enable non-interactive mode
2021-06-18 12:35:42 +02:00
fdb278838c
Merge pull request #881 from developandplay/patch-1
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Add --non-interactive option to simulation
2021-06-18 10:40:19 +02:00
5205356d24
tools/litex_json2dts: Simplify Switches interrupt support (and make it similar to other interrupts).
2021-06-18 10:36:33 +02:00
291374e66f
Merge pull request #854 from mczerski/gpio_dts_irq
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dts: gpio: interrupt controller definition for switches
2021-06-18 10:29:30 +02:00
98676162a3
VexRiscv-SMP: Review/Cleanup #906 .
2021-06-18 10:19:27 +02:00
58c533668c
Merge pull request #906 from rdolbeau/extra_config_and_dts
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Configurable [ID]TLB for VexRiscv & improved DTS
2021-06-18 10:09:28 +02:00
8ce7c583e6
cores/spi: Add Manual CS Mode (to allow doing Bulk Xfers without external changes), also cleanup/simplify a bit CSR descriptions.
2021-06-18 10:07:01 +02:00
ac73474d66
CONTRIBUTORS: Update.
2021-06-17 23:23:06 +02:00
a4be067d91
tools: Add litex_contributors.py script to easily update CONTRIBUTORS file.
2021-06-17 23:04:28 +02:00
7179d88e8c
ram/lattice_nx: Add init parameter and rename method to add_init.
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When init is not empty, call add_init automatically (similar to Memory).
2021-06-16 18:33:00 +02:00
869b5c24a8
Merge pull request #941 from danc86/nxlram-initval
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soc/cores/ram: allow populating initial values in Nexus LRAM
2021-06-16 18:31:00 +02:00
b0e6851150
Merge pull request #942 from zyp/external_software_packages
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Allow external software packages to be linked into the BIOS
2021-06-16 18:21:55 +02:00
aad64bbf9b
Merge pull request #943 from JosephBushagour/jbushagour_getargspec_fix
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Replace deprecated inspect.getargspec with inspect.getfullargspec.
2021-06-16 14:59:39 +02:00
deda54a9ba
Merge pull request #945 from tcal-x/symbiflow-make
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Force SymbiFlow 'make' to be non-parallel.
2021-06-16 14:57:36 +02:00
e59530ab50
Force SymbiFlow 'make' to be non-parallel.
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Signed-off-by: Tim Callahan <tcal@google.com>
2021-06-15 14:49:28 -07:00
8a644c9086
soc/add_video_xy: Allow passing phy or phy's Endpoint.
2021-06-15 18:10:24 +02:00
62ea48940a
Replace deprecated inspect.getargspec with inspect.getfullargspec.
2021-06-15 08:03:11 -05:00
8d527a1f3f
soc/software/bios: Allow registering init functions.
2021-06-13 14:04:34 +02:00
61636f1248
soc/integration/builder: Allow linking in external software packages.
2021-06-13 14:04:34 +02:00
be4c7cfb34
soc/cores/ram: allow populating initial values in Nexus LRAM
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On designs which use Nexus parts without any external memory, it can be
difficult to fit an embedded ROM program larger than a few KiB. Radiant
cannot infer LRAM, and refuses to infer EBRAM under many circumstances
too, so large memories tend to just consume a huge number of LUTs.
This patch makes it possible to explicitly wire up an LRAM as a ROM,
populate its initial values with a program, and execute directly from
it. That lets us embed programs up to 64KiB.
2021-06-11 16:41:10 +10:00
6b8a35a2f8
Merge pull request #940 from betrusted-io/keyclear_merge
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breakout the keyclearb pin for integration elsewhere
2021-06-11 04:46:08 +08:00
311b633a11
breakout the keyclearb pin for integration elsewhere
2021-06-11 04:44:39 +08:00
0a932be491
Merge pull request #936 from developandplay/patch-4
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Sync ROM_BOOT_ADDRESS with main_ram location
2021-06-09 12:11:24 +02:00
d5cfe09f4c
Merge pull request #931 from madscientist159/add-1920-1200-mode
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Add 1920x1200@60 RBv2 to LiteX video modes
2021-06-09 09:03:57 +02:00
8cdb0b8db3
Merge pull request #932 from developandplay/patch-3
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Fix base_address for LiteDRAMWishbone2Native
2021-06-09 08:58:28 +02:00
5061a368da
cores/video: Regroup VGA/DVI Phy in VideoGenericPHY and support variations (positive/negative hsync/vsync, etc...)
2021-06-09 08:49:29 +02:00
e0352a1f0f
Sync ROM_BOOT_ADDRESS with main_ram location
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Rocket and Blackparrot main_ram starts at 0x80000000
Vexriscv main_ram starts at 0x40000000
2021-06-09 03:36:32 +02:00
25ead1ad69
interconnect/stream: Add Gate.
2021-06-08 18:58:08 +02:00
bd1463514b
litex_setup: Remove Travis specific code (CI no longer run on Travis).
2021-06-08 10:49:28 +02:00
f2caeaf83a
Fix base_address for LiteDRAMWishbone2Native
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Fixes `origin == None` due to https://github.com/litex-hub/litex-boards/commit/ba01776
2021-06-08 00:51:11 +02:00
developandplay
enjoy-digital
Sylvain Munaut
Vegard Storheil Eriksen
Tim Callahan
Joey Bushagour
Dan Callaghan
bunnie