Sebastien Bourdeauducq
633e5e6747
fhdl/module/finalize: pass additional args to do_finalize
2013-03-30 11:29:46 +01:00
Sebastien Bourdeauducq
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq
77a0f0a3bb
actorlib/structuring/Cast: support inversion
2013-03-25 15:54:09 +01:00
Sebastien Bourdeauducq
c4c4765a4e
bank/csrgen/BankArray: retain name information
2013-03-25 14:44:15 +01:00
Sebastien Bourdeauducq
53edc3557e
bank/description/Register: add get_size
2013-03-25 14:43:44 +01:00
Sebastien Bourdeauducq
3da98ea04d
genlib/record: use getattr instead of __dict__
2013-03-24 00:51:01 +01:00
Sebastien Bourdeauducq
1897b74f97
genlib/record: add eq
2013-03-24 00:50:33 +01:00
Sebastien Bourdeauducq
9d7c679b8c
genlib/fifo: simple synchronous FIFO
2013-03-22 18:18:38 +01:00
Sebastien Bourdeauducq
ca431fc7c2
fhdl/module: support clock domain remapping of submodules
2013-03-22 18:17:54 +01:00
Sebastien Bourdeauducq
a94bf3b2c5
genlib/cdc/MultiReg: output clock domain defaults to sys
2013-03-21 10:40:02 +01:00
Sebastien Bourdeauducq
17f2b17654
fhdl/verilog: optionally disable clock domain creation
2013-03-18 18:45:19 +01:00
Sebastien Bourdeauducq
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq
dc55289323
fhdl/tools/_ArrayLowerer: complete support for arrays as targets
2013-03-18 14:38:01 +01:00
Sebastien Bourdeauducq
e95d2f4779
fhdl/tools/value_bits_sign: support not
2013-03-18 09:52:43 +01:00
Sebastien Bourdeauducq
b6fe3ace05
fhdl/structure: style fix
2013-03-17 15:33:38 +01:00
Sébastien Bourdeauducq
2a4cc3875c
Merge pull request #6 from larsclausen/master
...
Minor improvements
2013-03-17 07:33:14 -07:00
Sebastien Bourdeauducq
2f522bdd9f
genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
2013-03-15 19:50:24 +01:00
Sebastien Bourdeauducq
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
Sebastien Bourdeauducq
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
Sebastien Bourdeauducq
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
Sebastien Bourdeauducq
dd0f3311cd
structure: remove Fragment.call_sim
2013-03-15 19:15:48 +01:00
Sebastien Bourdeauducq
9b9bd77d00
sim: compatibility with new ClockDomain API
2013-03-15 19:15:28 +01:00
Sebastien Bourdeauducq
bd8bbd9305
Make ClockDomains part of fragments
2013-03-15 18:17:33 +01:00
Sebastien Bourdeauducq
5adab17efa
flow/actor/filter_endpoints: deterministic order
2013-03-14 12:20:18 +01:00
Sebastien Bourdeauducq
fc883198ae
bank/csrgen/BankArray: create banks in sorted order
2013-03-13 23:07:44 +01:00
Sebastien Bourdeauducq
52d13959f2
bank/description: modify reg/mem in-place
2013-03-13 19:46:34 +01:00
Lars-Peter Clausen
dea4674922
Allow SimActors to produce/consume a constant stream of tokens
...
Currently a SimActor requires one clock period to recover from consuming or
producing a token. ack/stb are deasserted in the cycle where the token is
consumed/produced and only re-asserted in the next cycle. This patch updates the
code to keep the control signals asserted if the actor is able to produce or
consume a token in the next cycle.
The patch also sets 'initialize' attribute on the simulation method, this will
make sure that the control and data signals will be ready right on the first
clock cycle.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 23:10:51 +01:00
Lars-Peter Clausen
72579a6129
Add support for negative slice indices
...
In python a negative indices usually mean start counting from the right side.
I.e. if the index is negative is acutal index used is len(l) + i. E.g. l[-2]
equals l[len(l)-2].
Being able to specify an index this way also comes in handy for migen slices in
some cases. E.g. the following snippet can be implement to shift an abitrary
length register n bits to the right:
reg.eq(Cat(Replicate(0, n), reg[-n:])
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2013-03-12 21:56:01 +01:00
Sebastien Bourdeauducq
69dbf84e54
sim/generic: support implicit get_fragment
2013-03-12 16:54:01 +01:00
Sebastien Bourdeauducq
ecfe1646ec
fhdl/verilog: implicit get_fragment
2013-03-12 16:16:06 +01:00
Sebastien Bourdeauducq
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq
04df076fba
bank: automatic register naming
2013-03-12 15:45:24 +01:00
Sebastien Bourdeauducq
7e2581bf17
fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
2013-03-12 13:48:09 +01:00
Sebastien Bourdeauducq
12158ceadf
fhdl/tracer: recognize LOAD_DEREF opcode
2013-03-12 10:31:56 +01:00
Sebastien Bourdeauducq
3c75121783
fhdl/tracer: remove leading underscores from names
2013-03-11 22:21:58 +01:00
Sebastien Bourdeauducq
80970b203c
bus/asmibus: use implicit finalization
2013-03-11 17:11:59 +01:00
Sebastien Bourdeauducq
b042757187
Fix Register name conflict between Pytholite and Bank
2013-03-10 19:47:21 +01:00
Sebastien Bourdeauducq
f93695f60e
bank/eventmanager: use module and autoreg
2013-03-10 19:29:05 +01:00
Sebastien Bourdeauducq
174e8cb8d6
bus/asmibus: use fhdl.module API
2013-03-10 19:28:22 +01:00
Sebastien Bourdeauducq
17e0dfe120
fhdl/module: replace autofragment
2013-03-10 19:27:55 +01:00
Sebastien Bourdeauducq
cddbc1157d
bank/description/AutoReg: check that get_memories and get_registers are callable
2013-03-10 18:11:29 +01:00
Sebastien Bourdeauducq
68fe4c269c
bank/csrgen: BankArray
2013-03-10 00:45:16 +01:00
Sebastien Bourdeauducq
f1474420df
bank/description: AutoReg
2013-03-10 00:43:16 +01:00
Sebastien Bourdeauducq
d0676e2dd1
migen/fhdl/autofragment: factorize
2013-03-09 23:23:24 +01:00
Sebastien Bourdeauducq
d0d2df3c4b
fhdl/autofragment: remove legacy functions
2013-03-09 23:05:45 +01:00
Sebastien Bourdeauducq
72fb6fd6bd
fhdl/tools/flat_iteration: generalize
2013-03-09 23:03:15 +01:00
Sebastien Bourdeauducq
f53acb92e7
fhdl/autofragment: fix submodules
2013-03-09 21:15:38 +01:00
Sebastien Bourdeauducq
6da8eb906f
fhdl/autofragment: empty build_fragment by default
2013-03-09 19:10:47 +01:00
Sebastien Bourdeauducq
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
Sebastien Bourdeauducq
b75fb7f97c
csr/SRAM: support for writes with memory widths larger than bus words
2013-03-09 00:50:57 +01:00
