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9876 Commits

Author SHA1 Message Date
Richard Tucker 5504cc626f soc/cores/i2c: change ISR to rising edge of idle 2024-07-20 15:45:44 +10:00
Richard Tucker b8b6ecef7c soc/cores/i2c: fix CSR generation 2024-07-20 15:45:44 +10:00
Andrew Dennison 90128756f9 test_i2c: test reading config 2024-07-20 15:45:44 +10:00
Andrew Dennison ad37e17743 soc/cores/i2c: add interrupt 2024-07-20 15:45:44 +10:00
Andrew Dennison 4ddab34714 test_i2c: generate i2c.vcd 2024-07-20 15:45:44 +10:00
Andrew Dennison a079da922a soc/cores: adapt misoc i2c to litex 
Also add misoc license information.
 2024-07-20 15:45:44 +10:00
Andrew Dennison 9dc3eefb7d soc/cores/i2c: import from misoc 
* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
 2024-07-20 15:45:44 +10:00
Florent Kermarrec a014c4f07c tools/litex_sim: Cleanup imports. 2024-07-18 12:16:23 +02:00
Dolu1990 8a08d5ca19
Merge pull request #2017 from Dolu1990/vexiiriscv 
Fix VexiiRiscv
 2024-07-18 11:37:03 +02:00
Dolu1990 cbe7413fee Fix VexiiRiscv 2024-07-18 11:32:07 +02:00
enjoy-digital 1b9bdbdce4
Merge pull request #2016 from Dolu1990/vexiiriscv 
Update VexiiRiscv
 2024-07-18 11:27:20 +02:00
Dolu1990 f687425cb1 Update VexiiRiscv 2024-07-18 11:26:13 +02:00
Dolu1990 473784581d
Merge pull request #2011 from Dolu1990/vexiiriscv 
cpu: Vexii/Nax fmax / area improvements
 2024-07-12 17:29:45 +02:00
Dolu1990 9fa1b4c123 Update Nax/Vexii 2024-07-12 16:17:30 +02:00
inc aef5a2094e soc/cores/video: Add additional color formats 2024-07-10 15:21:51 +02:00
Dolu1990 22ff3ac42d Merge branch 'master' into vexiiriscv 
# Conflicts:
#	litex/soc/cores/cpu/vexiiriscv/core.py
 2024-07-10 09:37:43 +02:00
Dolu1990 1267ba8ae6 Update Nax/Vexii 2024-07-10 09:35:34 +02:00
Florent Kermarrec e4e9bd2125 interconnect/axi/axi_lite: Add bursting property even if always False. 2024-07-09 17:02:54 +02:00
Dolu1990 372ab25273 Merge branch 'nax64_irq' into vexiiriscv 2024-07-09 15:18:25 +02:00
Florent Kermarrec 549d23e4f7 build/efinix: Add default parameter values and fix other typos. 2024-07-09 10:04:03 +02:00
Florent Kermarrec e6171e79db build/efinix: Fix typos (thanks @AndrewD). 2024-07-09 10:00:21 +02:00
enjoy-digital 7de4f01aa8
Merge pull request #2009 from trabucayre/efinix_args_opts 
build/efinix: added argument to change synthesis options configurations
 2024-07-08 17:01:28 +02:00
Gwenhael Goavec-Merou ec1528fb69 build/efinix: added argument to change synthesis options configurations 2024-07-08 15:59:30 +02:00
Florent Kermarrec 0db650ac6a soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic). 2024-07-05 13:56:14 +02:00
Florent Kermarrec 3c2ddd1655 cores/can/ctu_can_fd: Remove pads.irq that was used as debug. 2024-07-05 09:34:36 +02:00
enjoy-digital 7ec35eb4c5
Merge pull request #2007 from enjoy-digital/ctu-can-fd 
Add initial CTU-CAN-FD core support.
 2024-07-05 09:16:21 +02:00
enjoy-digital d838a9ca73
Merge pull request #2006 from trabucayre/update_altera_build 
Update altera build
 2024-07-04 13:04:15 +02:00
Gwenhael Goavec-Merou 9fd63973aa build/altera/quartus.py: added support for ips other than QSYS_FILE 2024-07-04 09:51:09 +02:00
Gwenhael Goavec-Merou 7393c35264 build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn 2024-07-04 09:50:06 +02:00
enjoy-digital b286fe5621
Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs 
litex_json2dts_zephyr.py: Remove unnessesary configs
 2024-07-04 09:10:27 +02:00
Florent Kermarrec d4d1a1bfd7 gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog. 2024-07-03 21:44:31 +02:00
Florent Kermarrec aac828b4cb soc/add_etherbone: Update ethmac. 2024-07-02 17:10:32 +02:00
Fin Maaß b285992fb1 litex_json2dts_zephyr.py: Remove unnessesary configs 
Remove all configs, that are enabled by default
in zephyr based on the devicetree.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-07-02 15:04:50 +02:00
Florent Kermarrec 2a83bce63e cores/dma: Automatically call add_ctrl method in add_csr is ctrl are not present. 2024-07-01 18:22:41 +02:00
Florent Kermarrec 9c07b45f3c soc/add_ethernet: Add 64-bit data_width support. 2024-06-27 09:35:28 +02:00
enjoy-digital 3dd3477ea2
Merge pull request #2004 from enjoy-digital/wishbone_dma_ctrl 
Wishbone DMA: Split add_csr() method in add_ctrl()/add_csr().
 2024-06-26 18:46:01 +02:00
Florent Kermarrec 4b745f9eba soc/cores/dma: Add default parameters to add_ctrl. 2024-06-26 17:57:47 +02:00
Florent Kermarrec 01a15e4bbf soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. 2024-06-26 16:13:45 +02:00
Florent Kermarrec 23a0d8fa2a soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic. 2024-06-26 16:07:12 +02:00
enjoy-digital 06a26b7c9b
Merge pull request #2003 from enjoy-digital/liteeth_wishbone_tx_rx_buses 
integration/soc/add_ethernet: Use separates TX/RX buses/regions for e…
 2024-06-25 19:05:49 +02:00
Florent Kermarrec 14a640302c integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. 
LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161.
 2024-06-25 17:39:26 +02:00
Florent Kermarrec 1ad0f828bb soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design. 2024-06-25 15:07:37 +02:00
Florent Kermarrec 462016a1d0 litex/tools/litex_json2dts_linux: Add initial CAN support. 2024-06-24 13:01:18 +02:00
Florent Kermarrec 71ff4eaadc soc/cores/can: Switch to our fork of CTU-CAN-FD, remove debug signals and do a git clone if not present in execution directory. 2024-06-24 12:53:38 +02:00
Florent Kermarrec bad64bcf6d soc/cores: Add initial CTU-CAN-FD integration from 2021 work with recent updates/tests. 2024-06-24 12:27:17 +02:00
Florent Kermarrec 8afa36f24a CHANGES.md: Update and add Issue/PR number. 2024-06-24 10:52:34 +02:00
enjoy-digital a47dde6fbc
Merge pull request #1999 from FlyGoat/csr-re 
csr_bus: Honour re signal from the upstream bus
 2024-06-24 10:36:48 +02:00
enjoy-digital 8e4f8781f7
Merge pull request #1996 from VOGL-electronic/litex_watchdog 
core: add watchdog feature
 2024-06-24 10:32:48 +02:00
enjoy-digital 11537ec8cc
Merge pull request #2001 from rtucker85/master 
liblitespi: fix xor-used-as-pow bug
 2024-06-24 09:05:34 +02:00
enjoy-digital 21674ee29c
Merge pull request #1998 from FlyGoat/ahb-fixes 
soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
 2024-06-24 09:04:33 +02:00