65a0b12812
actorlib/spi/DMAController: export length/storage/trigger
2013-07-13 17:13:15 +02:00
6595b9a111
actorlib/spi/SingleGenerator: export CSRs
2013-07-13 17:12:51 +02:00
c2d6f14087
flow/actor/PipelinedActor: clean up
2013-07-12 18:52:34 +02:00
6aa1e0c199
actorlib/spi/DMAWriteController: len -> flen
2013-07-11 19:22:56 +02:00
f5ddd33e7e
dfi: split phase description
2013-07-10 19:56:47 +02:00
1d33c61308
examples/sim/abstract_transactions_lasmi: check data
2013-07-10 19:11:02 +02:00
43fe16ef73
bus/lasmibus: add separate req/data ack to target and initiator
2013-07-10 19:09:51 +02:00
af6ef0a3b4
dma_lasmi/Writer: fix default FIFO depth
2013-07-07 20:01:55 +02:00
fa8112c3f5
dma_lasmi/Reader: handle ack=1 when stb=0
2013-07-07 18:57:05 +02:00
7e6fbd31a4
lasmibus/crossbar: simplify master ack generation
2013-07-07 18:56:43 +02:00
b68c00d36f
pytholite: fix kwargs handling
2013-07-03 17:20:05 +02:00
4096a785f9
examples/pytholite/basic: demonstrate generator arguments
2013-07-03 16:35:24 +02:00
0aa58f5dcf
pytholite: support generator arguments
2013-07-03 16:35:07 +02:00
04efee7847
fhdl: mark variable as deprecated
2013-06-30 20:14:20 +02:00
6420b56908
examples/complex: do not use variable
2013-06-30 19:27:01 +02:00
71b89e4c46
fhdl/verilog: lower complex slices before reset insertion
2013-06-30 14:32:47 +02:00
ded5e569eb
fhdl/tools: separate complex slice lowerer from basic lowerer
2013-06-30 14:32:19 +02:00
9c59ea1e26
genlib/misc: remove bitreverse
2013-06-30 14:31:25 +02:00
a255296171
support re-slicing and non-unit step size
...
* support slicing of Slice/Cat/Replicate through lowering
* support non-unit step size slices through unpacking and Cat()
2013-06-30 14:03:34 +02:00
9d241f8cd3
coding.py: rewrite If() to make verilog more readable
2013-06-30 11:39:47 +02:00
b0d467d744
pytholite: use eval instead of literal_eval
2013-06-28 19:03:55 +02:00
ecc4062071
genlib/coding.py: binary vs. one-hot, priority coding
2013-06-28 15:20:01 +02:00
48a5b86dcd
genlib/cordic: cleanup
2013-06-26 22:46:04 +02:00
080afdc3f9
fhdl/verilog: fix signedness rules for comparison
2013-06-26 22:45:47 +02:00
0224ea01cb
migen/genlib/cordic.py: generic cordic
...
* rotating or vectoring cordic modes
* circular, linear, or hyperbolic functions
* combinatorial, pipelined or iterative evaluation
* arbitrary width, stages and guard bits
* two or four quadrant mode for circular/rotate
2013-06-26 22:31:36 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
b56cb3cefc
fhdl/verilog: improve error reporting
2013-06-24 19:44:25 +02:00
d6f7b4cee6
lasmi: separate request and data ack to support bankmachine FIFOs (buggy/incomplete)
2013-06-17 23:36:03 +02:00
5cd0019231
genlib/fifo: support records
2013-06-17 23:35:10 +02:00
6d6d232cad
lasmibus/crossbar: better switching policy
2013-06-15 16:51:09 +02:00
ac2cde0e87
asmibus: remove port sharing
2013-06-14 18:34:36 +02:00
0c52c08989
bus/asmibus: fix slot aging timer
2013-06-14 17:57:43 +02:00
1ec1fb9ebe
bus/lasmibus/Crossbar: support cba_shift=0
2013-06-11 18:15:49 +02:00
fe54c68762
lasmi: fix minor problems
2013-06-10 22:49:33 +02:00
aea3b59432
genlib/fsm: fix handling of zero delayed_enter
2013-06-10 22:49:05 +02:00
3a284b9c1e
actorlib: LASMI DMA (untested)
2013-06-10 22:29:39 +02:00
932bfa7e75
bus: Wishbone -> LASMI bridge (untested)
2013-06-10 18:52:07 +02:00
9f560cb758
examples/sim: add LASMI demo
2013-06-09 23:36:51 +02:00
f2e2397c9d
bus/lasmibus: bugfixes
2013-06-09 23:36:32 +02:00
a836cba790
bus/lasmibus: add target and initiator
2013-06-09 16:03:22 +02:00
2948f6a16a
examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI
2013-06-09 14:17:30 +02:00
35f9f2e9d7
bus/lasmi: interface definition and crossbar (untested)
2013-06-08 15:49:50 +02:00
85813b3b58
csr/sram: fix reads on high addresses when word_bits != 0
2013-06-03 21:52:23 +02:00
e5e3492afe
csr/sram: fix page_bits computation
2013-06-03 21:51:44 +02:00
cebfe787db
genlib/misc: fix import
2013-05-30 18:46:52 +02:00
ebbd5ebcd2
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
2013-05-30 18:45:04 +02:00
f0b0942055
bitreverse: fhdl/tools -> genlib/misc
2013-05-30 18:44:37 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jördens
Kenneth Ryerson