b356204f95
soc_core: add JTAG UART support (uart_name="jtag_uart)
2019-09-06 11:56:42 +02:00
d0ebbda4b3
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
2019-09-06 11:55:41 +02:00
2638393b53
soc_zynq: fix indent
2019-09-05 15:59:35 +02:00
9051cf97e4
soc_zynq: fix typo
2019-09-05 15:55:18 +02:00
67a09aef05
soc/interconnect/stream: add Monitor module
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Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
2019-09-05 11:54:14 +02:00
6f150a5626
Merge pull request #254 from mithro/crc-smaller
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Add @xobs' smaller CRC version
2019-09-03 07:23:32 +02:00
2a41f0d2a4
Use `SMALL_CRC` to enable smaller CRC versions.
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@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
2019-09-02 14:48:30 -07:00
083337441a
Remove extra whitespace.
2019-09-02 14:47:20 -07:00
c0e723868e
libbase: crc16: commit smaller version of crc16
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
a59d0efca0
libbase: crc32: add smaller version
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:44:18 -07:00
27c334d440
Merge pull request #252 from mithro/only-change-on-contents
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Only write file if contents will change.
2019-09-02 14:42:22 -07:00
3ff6a18a45
Only write file if contents will change.
2019-09-02 14:26:41 -07:00
a2938a7ae7
soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic"
2019-08-31 18:34:08 +02:00
19d3acfc71
Merge pull request #251 from micro-FPGA/master
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atlantic JTAG UART working module
2019-08-31 18:33:27 +02:00
fb00ee85a2
Create atlantic.py
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atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
2019-08-30 09:35:10 +02:00
41fe7cae0b
core/spi: add minimal SPISlave
2019-08-29 09:46:20 +02:00
b845755995
gen/fhdl/verilog: allow single element verilog inline attribute
2019-08-28 05:24:11 +02:00
5a7b4c3406
targets/nexys_video: generate clk100
2019-08-27 14:06:13 +02:00
c179741cf3
software/bios: switch to standard CRLF
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Avoid setting terminal to "implicit CR in every LF" mode.
2019-08-27 09:45:44 +02:00
0328ba7d6c
tools/litex_term: add automatic check to see if we need to insert LF or not
2019-08-26 18:17:43 +02:00
ffebd2076c
bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available)
2019-08-26 17:15:01 +02:00
4842bdcf08
tools/litex_term: add sdl_payload_length
2019-08-26 12:10:11 +02:00
3e30c64842
litex_setup: add litex-boards
2019-08-26 09:28:58 +02:00
d79cd87dd6
Merge pull request #246 from gsomlo/gls-native-rv64
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software: use native toolchain for same host, target architectures
2019-08-23 21:36:51 +02:00
6d844a038a
software: use native toolchain for same host, target architectures
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LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-23 09:04:55 -04:00
d36f1fb7d2
Merge pull request #244 from atommann/master
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changing http to https
2019-08-17 11:54:39 +02:00
a45dbee54f
changing http to https
2019-08-17 16:02:10 +08:00
92e5b4b2cd
Merge pull request #2 from enjoy-digital/master
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update with hyperram and other changes
2019-08-16 14:36:59 +02:00
4990bf33c0
soc/core: simplify/cleanup HyperRAM core
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- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
f47e4978f2
libero enable enhanced constraints
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Libero 12.0 does not support any more classic constraint flow
2019-08-16 10:31:53 +02:00
d1502d4195
soc/cores: add initial simple hyperram core
2019-08-16 09:48:17 +02:00
6e6fe83af3
build/altera/quartus: add add_ip method to use Quartus QSYS files
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platform.add_ip("my_ip.qsys")
2019-08-15 13:45:29 +02:00
2899928aba
cpu_interface: add json csr map export, simplify csv csr map export using json
2019-08-15 09:27:33 +02:00
9d4b7cd515
bios/sdram: set init done after memtest (for standalone LiteDRAM controllers)
2019-08-14 19:09:58 +02:00
0cd4e45f48
build/xilinx/vivado: use "" for strings
2019-08-14 19:03:10 +02:00
8d161a47cf
build/xilinx/vivado: remove with_phys_opt
2019-08-14 19:02:01 +02:00
f6638ded13
Merge pull request #243 from sergachev/master
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build/xilinx/vivado: improve directive support
2019-08-14 18:58:15 +02:00
ccc2cbd9d4
Merge pull request #241 from railnova/zynq
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[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 18:55:34 +02:00
861eea8a07
build/xilinx/vivado: improve directive support
2019-08-14 17:49:13 +02:00
db4c609a33
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
2019-08-14 11:30:39 +02:00
6d5fddc160
cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
2019-08-14 07:35:45 +02:00
383c05e239
Merge pull request #240 from danielkucera/patch-1
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more understandable error when missing a memory
2019-08-13 10:34:50 +02:00
a5eaf172c5
more understandable error when missing a memory
2019-08-13 10:14:16 +02:00
1d957d7a31
Update .gitmodules
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http to https
2019-08-12 22:20:34 +08:00
2b815f7096
Merge pull request #235 from gsomlo/gls-trellis-yosys-opt
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build/lattice/trellis: use additional yosys optimization flags
2019-08-10 15:33:05 +02:00
6c298cb708
build/lattice/trellis: use abc9 techmapping pass with yosys
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-09 09:12:22 -04:00
31bfb54667
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys
2019-08-09 13:26:31 +02:00
e670cb9176
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
2019-08-09 12:33:10 +02:00
6d94c07d70
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
2019-08-09 10:33:42 +02:00
0c287b11ba
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
2019-08-09 09:27:32 +02:00
Florent Kermarrec
Tim 'mithro' Ansell
Sean Cross
Antti Lukats
Gabriel L. Somlo
atommann
Ilia Sergachev
chmousset
Daniel Kucera