6f8a0052ef
soc/software/liblitedram: fix pattern checking for low DFI databits
2021-08-04 15:14:07 +02:00
4636a841d3
build/sim/gtkwave: automate handling of Endpoint and other stream primitives
2021-07-22 15:49:20 +02:00
751e99690e
Merge pull request #965 from thirtythreeforty/ecp5-pll-x4
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ECP5PLL: implement 4-output solver
2021-07-21 19:08:18 +02:00
a782596513
Merge pull request #975 from cklarhorst/master
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soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode
2021-07-21 11:57:21 +02:00
e17a010866
soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode
2021-07-20 22:08:36 +02:00
c64c6e4056
cpu/blackparrot: Re-map csr and keep the lower 128MBs for the SoC IO auto-allocation.
2021-07-20 12:05:54 +02:00
1bf7abfc8a
Merge pull request #970 from trabucayre/openfpgaloader_check_type
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openfpgaloader: improves freq conversion type
2021-07-19 09:58:21 +02:00
e3f577e0be
openfpgaloader: improves freq conversion type
2021-07-17 17:02:22 +02:00
e0d5a7bff5
interconnect/packet/Packetizer/Depacketizer: Avoid generating unaligned logic when aligned.
2021-07-15 19:00:50 +02:00
0a919e709f
interconnect/packet: Improve PacketFIFO to handle payload/param separately.
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Useful to save resources and store Stream's params more efficiently.
2021-07-15 18:06:03 +02:00
b2f8fa5464
gen/fhdl/verilog: Make DummyAttrTranslate a dict.
2021-07-15 16:48:24 +02:00
bf52c1083f
Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_options
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openfpgaloader: add cable and freq options
2021-07-15 12:18:01 +02:00
730b57d9cd
build/gowin: Add initial timing constraints support.
2021-07-15 11:06:03 +02:00
10ea45da55
build/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl.
2021-07-15 10:01:52 +02:00
2b393254da
build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed).
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Most of the attributes are Xilinx specific, it does not make sense to provide them on other FPGA devices.
2021-07-15 09:59:15 +02:00
bdc32171fd
gen/fhdl/verilog/_printattr: Avoid trying translating attribute when not supported by Toolchain.
2021-07-15 09:57:15 +02:00
4fd974be10
build/gowin: Minor cleanups.
2021-07-15 09:36:41 +02:00
3706ed7416
openfpgaloader.py: cast int to str
2021-07-14 17:50:50 +02:00
c984a4dbc8
openfpgaloader: add cable and freq options
2021-07-14 16:48:29 +02:00
756503ab92
clock/gowin_gw1n: Add Initial On-Chip Oscillator support.
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Ex: self.submodules.osc = GW1NOSC(device="GW1N9K", freq=10e6)
2021-07-14 11:42:35 +02:00
6fc87f7c85
build/gowin/common: Add DDRInput/DDROutput implementations.
2021-07-14 10:01:54 +02:00
a8cea15b95
cores/clock/gowin_gw1n/create_clkout: Add reset support (through AsyncResetSynchronizer) and enable it by default.
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Should be based on PLL's lock but does not seem stable, so use reset input for now.
2021-07-14 09:38:23 +02:00
cfbc06c297
build/gowin/common: Add AsyncResetSynchronizer implementation.
2021-07-14 09:37:00 +02:00
fab6512928
Merge pull request #967 from JosephBushagour/jbushagour_assembly_interoperability
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Make "generated/soc.h" able to be included in assembly files.
2021-07-13 10:47:59 +02:00
df67b65a0a
Merge pull request #957 from pftbest/fix_fst
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Fix compile error when FST traces are enabled on macOS.
2021-07-13 10:38:40 +02:00
c79e428fe1
Add soc.h interoperability with assembly.
2021-07-12 08:33:17 -05:00
bc77aa37f0
include/hw/common: Fix _csr_rd_buf/_csr_wr_buf for sizeof(buf[0]) < CSR_DW_BYTES case.
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- Shift in _csr_rd_buf should only been done when buf is set.
- When CSR size is not an exact multiple of the CSR data-width, the gap is in
the low addresses, not the high ones. So offset is introduced to take this into
account.
2021-07-09 17:36:17 +02:00
b29a99cd0b
liblitedram/sdram.c: Fix DFII_PIX_DATA_BYTES computation.
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DFII CSR size is not necessarily multiple of 4 (often the case but not with ECC for example).
2021-07-09 17:32:43 +02:00
8954041a93
clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
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Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this. Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
2b49430f2c
README.md: Rewrite Welcome section and update copyright.
2021-07-08 12:08:24 +02:00
9a51dfb50e
tools/litex_sim: Let the SDRAMPHYModel pick default settings.
2021-07-08 09:09:57 +02:00
fced79631e
tools/litex_sim: sdram_module_nphases/get_sdram_phy_settings now directly integrated in litedram.phy.model.
2021-07-08 09:01:32 +02:00
34ba649f38
clock/lattice_ecp5/ECP5PLL: implement 4-output solver
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Reimplement the configuration loop to allow all 4 outputs to be used by
the user, if one of them is suitable for use as VCO feedback.
The new strategy is to first iterate over requested outputs to see if
any of them can be used as a feedback source. If one can, it is
selected, and if no output is suitable, it attempts to instantiate one.
Once the feedback path is selected, the VCO frequency is known and it
attempts to calculate the remaining outputs' settings.
In addition, this implementation now respects datasheet limits in two
new ways:
- It respects the post-input-divider minimum frequency of 10MHz
- It respects the max output frequency of 400MHz for instantiated
feedback outputs
I am slightly unhappy with the seemingly-repetitive for loops. However
each one has slightly different sematics and I don't see a way to
combine them that doesn't hinder readability.
2021-07-07 01:15:06 -05:00
dd5413bc9f
Merge pull request #964 from niw/increase_macos_ttyusbmodem_delay
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Increase delay for `tty.usbmodem` on macOS.
2021-07-06 18:51:28 +02:00
8b9f03efba
clock/lattice_ecp5/ECP5PLL: Expose standby signal
2021-07-06 08:40:36 -05:00
0953c52eea
Increase delay for `tty.usbmodem` on macOS.
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**Problems**
On macOS USB CDC ACM, which appears as `/dev/tty.usbmodem*`,
somehow `lxterm` keeps failing to send a payload.
**Solution**
Increase delay.
It's very unknown why to me, however, probably macOS USB CDC ACM
driver implementation issue.
**Testing**
Tested on MacBook Air (2020, M1) for OrangeCrab (rev.0.2) target
with Linux on LiteX SoC bitstream build from current commit and
load prebuild Linux On LiteX image.
2021-07-05 11:46:57 -07:00
f9f1b8e25d
liblitedram: Consider 1s window is valid when indirectly seen before 0 (start at 0 and long enough).
2021-06-29 12:03:51 +02:00
8192ad335f
Merge pull request #958 from sergachev/master
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soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite
2021-06-28 17:37:29 +02:00
65babd6500
soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite
2021-06-28 11:50:45 +02:00
4d959bbc81
Merge pull request #956 from developandplay/simplify-blackparrot-setup
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Simplify blackparrot setup
2021-06-28 11:26:50 +02:00
35204225e8
Fix compile error when FST traces are enabled on macOS.
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Compile options should be the same for all platforms.
2021-06-27 17:34:43 +03:00
9fd9eaea07
Move patch script to python-data
2021-06-27 01:31:05 +02:00
ac217d818f
Set environmental variables in python
2021-06-27 01:07:27 +02:00
e3f6d8349b
Use os methods to expand env vars
2021-06-26 16:30:54 +02:00
b787ee4411
Move systemverilog files to python-data
2021-06-26 15:45:48 +02:00
16b3e08c17
Copy config loader in python
2021-06-26 15:37:17 +02:00
23afca3de8
Merge pull request #953 from developandplay/blackparrot-32bit-csr
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Blackparrot 32bit csr
2021-06-23 19:20:51 +02:00
edc4c85615
build/lattice/common: Add ECP5 Differential Output support.
2021-06-23 11:55:22 +02:00
adb71bde8c
Adjust wishbone adapter for 32bits
2021-06-22 23:37:24 +02:00
b795f848a2
Fixup blackparrot
2021-06-22 18:43:17 +02:00
Jędrzej Boczar
enjoy-digital
Christian Klarhorst
Gwenhael Goavec-Merou
Joey Bushagour
George Hilliard
Yoshimasa Niwa
Ilia Sergachev
Vadzim Dambrouski
developandplay