Florent Kermarrec
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6b93849a08
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gensoc: parameter check is now more restrictive, add additional info to help user
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2015-02-28 03:12:00 +01:00 |
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Florent Kermarrec
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8e04ef7b95
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test minicon with de0nano (OK) and fix missing self in gensoc
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2015-02-27 20:00:16 +01:00 |
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Florent Kermarrec
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f1200d6388
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gensoc: move I/O for rom initialization to make.py
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2015-02-27 19:48:07 +01:00 |
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Florent Kermarrec
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074f576340
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targets: add de0nano (100MHz, integrated bios and SDRAM)
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2015-02-27 19:47:32 +01:00 |
|
Florent Kermarrec
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cb38580400
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make.py fix indent
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2015-02-27 18:58:36 +01:00 |
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Florent Kermarrec
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5e2e9338d2
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bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
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2015-02-27 17:22:44 +01:00 |
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Florent Kermarrec
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b031c5edae
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targets: fix MiniSoC
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2015-02-27 17:12:37 +01:00 |
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Florent Kermarrec
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e07e124118
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sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir
We will maybe move things, but at least it's in MiSoC now
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2015-02-27 17:07:44 +01:00 |
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Florent Kermarrec
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e82531cdf8
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move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
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2015-02-27 16:54:22 +01:00 |
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Florent Kermarrec
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07b9cabd0d
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gensoc: make it more generic (a SoC does not necessarily have a CPU)
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2015-02-27 16:39:00 +01:00 |
|
Florent Kermarrec
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367db268ad
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reserve csr_map 0-->16 for gensoc internal csrs
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2015-02-27 14:18:13 +01:00 |
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Florent Kermarrec
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be0eb8d265
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use cachesize reported in wishbone2lasmi
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2015-02-27 14:13:38 +01:00 |
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Florent Kermarrec
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225a2d4704
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report cachesize in wishbone2lasmi
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2015-02-27 14:12:13 +01:00 |
|
Florent Kermarrec
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9814001c79
|
create cpu dir and move lm32/mor1kx in it
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2015-02-27 10:51:03 +01:00 |
|
Florent Kermarrec
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9f636f7985
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move memtest to sdram
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2015-02-27 10:47:54 +01:00 |
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Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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e4de5a0c9d
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make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
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2015-02-27 10:23:17 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
|
Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
|
Florent Kermarrec
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54a8a52e90
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xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
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2015-02-27 09:05:23 +01:00 |
Robert Jordens
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2b0937153d
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xilinx/programmer: fix xc3sprog (GenericProgrammer)
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2015-02-26 21:36:15 -07:00 |
|
Robert Jordens
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2b12679ef6
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add pipistrello target
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2015-02-26 21:35:42 -07:00 |
|
Robert Jordens
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8de5b947bd
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pipistrello: use fpgaprog
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2015-02-26 21:34:02 -07:00 |
|
Robert Jordens
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ca52aa5b8c
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add fpgaprog programmer
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2015-02-26 21:33:49 -07:00 |
|
Robert Jordens
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5b5d2d15b8
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add pipistrello platform
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2015-02-26 21:33:42 -07:00 |
Sebastien Bourdeauducq
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ba26a400e3
|
Merge branch 'master' of https://github.com/m-labs/migen
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2015-02-26 21:32:39 -07:00 |
|
Robert Jordens
|
c9ed38dec8
|
gensoc: missing self.
|
2015-02-26 21:32:11 -07:00 |
|
Sebastien Bourdeauducq
|
a3909bb5e2
|
Merge branch 'master' of https://github.com/m-labs/misoc
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2015-02-26 21:28:12 -07:00 |
|
Sebastien Bourdeauducq
|
28c219ebd2
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platforms/kc705: add user SMA clock
|
2015-02-26 16:22:22 -07:00 |
Yann Sionneau
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8364fe6674
|
target/kc705: allow access to pll_sys signal before BUFG
|
2015-02-26 15:56:10 -07:00 |
|
Yann Sionneau
|
dbdb263acc
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mibuild/kc705: add missing pins on FMC LPC
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2015-02-26 15:54:41 -07:00 |
|
Florent Kermarrec
|
09fbbca53e
|
gensoc: cpus now directly add their verilog sources
|
2015-02-26 20:49:21 +01:00 |
|
Florent Kermarrec
|
5e8a0c496d
|
gensoc: add mem_map and mem_decoder to avoid duplications
|
2015-02-26 20:12:27 +01:00 |
|
Florent Kermarrec
|
5ac5ffe359
|
gensoc: get platform_id from platform
|
2015-02-26 19:07:19 +01:00 |
|
Florent Kermarrec
|
8da1faf310
|
mibuild: move identifier to platforms
|
2015-02-26 19:00:43 +01:00 |
|
Florent Kermarrec
|
e6a21b2305
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mibuild: fix missing xilinx_common -->xilinx.common change
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2015-02-26 14:04:36 +01:00 |
|
Florent Kermarrec
|
554731ae44
|
targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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2015-02-26 13:08:15 +01:00 |
|
Florent Kermarrec
|
bd5ed0977b
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platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)
|
2015-02-26 12:51:57 +01:00 |
|
Florent Kermarrec
|
e27a94e7fc
|
mibuild: add VivadoProgrammer (only load_bitstream)
|
2015-02-26 12:31:19 +01:00 |
|
Florent Kermarrec
|
b3faf5f0da
|
mibuild: better file organization (create directory for each vendor and move programmers in it)
|
2015-02-26 12:25:59 +01:00 |
|
Florent Kermarrec
|
02b3f51382
|
liteeth: fix example_designs generation
|
2015-02-26 10:23:38 +01:00 |
|
Florent Kermarrec
|
00862a383c
|
liteeth: fix import (from liteeth --> from misoclib.liteeth)
|
2015-02-26 09:48:37 +01:00 |
|
Florent Kermarrec
|
60effe1d95
|
move files to liteeeth and create example_designs directory
|
2015-02-26 09:35:14 +01:00 |
|
Sebastien Bourdeauducq
|
0267868cbe
|
remove litex submodule
|
2015-02-25 10:40:44 -07:00 |
|
Sebastien Bourdeauducq
|
658cb0e405
|
merge liteeth
|
2015-02-25 10:35:39 -07:00 |
|
Sebastien Bourdeauducq
|
8015d12692
|
move files for misoc integration
|
2015-02-25 10:34:11 -07:00 |
|
Florent Kermarrec
|
eef679b6d4
|
phy/sim: generate sop/eop
|
2015-02-25 17:47:44 +01:00 |
|
Florent Kermarrec
|
a559fc77c8
|
remove upload optimization (we will use wishbone later for performance)
|
2015-02-24 18:01:04 +01:00 |
|
Florent Kermarrec
|
6b7026f521
|
add sim phy
|
2015-02-24 01:42:56 +01:00 |
|
Florent Kermarrec
|
b6ebcece95
|
add read grouping to etherbone, we now have interesting upload speeds... :)
|
2015-02-23 18:58:31 +01:00 |