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Author SHA1 Message Date
Sebastien Bourdeauducq
71c2c5813b platforms/mixxeo: remove bank 3 DVI inputs 2013-07-04 19:27:28 +02:00
Sebastien Bourdeauducq
0883e99de3 Do not specify period constraints twice 2013-07-04 19:25:29 +02:00
Sebastien Bourdeauducq
0784cd164f Add Mixxeo platform 2013-07-04 19:23:25 +02:00
Sebastien Bourdeauducq
1f3c941a78 platforms/m1: move generic platform commands to do_finalize 2013-07-04 19:22:59 +02:00
Sebastien Bourdeauducq
7e4552bbfc lx9_microboard: improve compat with other boards 2013-06-27 19:30:57 +02:00
Robert Jordens
c1cf37f05a add Avnet Spartan6 LX9 Micrboard platform 2013-06-27 19:18:47 +02:00
Robert Jordens
e233c62d27 * generic_platform.py: add a finalize() method 
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
 2013-06-27 19:17:02 +02:00
Sebastien Bourdeauducq
6b56428a21 Shorter multipin signal definition 2013-06-25 22:57:31 +02:00
Sebastien Bourdeauducq
953e603915 xilinx_ise: improve parameter passing 2013-06-01 17:22:57 +02:00
Sebastien Bourdeauducq
548f2685bb platform/rhino: rename ismm data out signal to locked 2013-05-30 11:06:02 +02:00
Sebastien Bourdeauducq
759858f739 Use migen.fhdl.std 2013-05-26 18:07:26 +02:00
Sebastien Bourdeauducq
c13e573e9f Require Python 3.3 2013-05-26 18:02:18 +02:00
Sebastien Bourdeauducq
e272e68fac platforms/papilio_pro: swap tx/rx to be consistent with M1 2013-05-19 20:24:47 +02:00
Sebastien Bourdeauducq
fe64ade1ac platforms/m1: add pots pins 2013-05-13 15:38:20 +02:00
Sebastien Bourdeauducq
7a2f31b2e8 platforms/papilio_pro: no reset signal by default 2013-05-07 19:10:18 +02:00
Sebastien Bourdeauducq
439f032921 crg: support for resetless system clock domain 2013-05-07 19:09:56 +02:00
Florent Kermarrec
6a4c194aab platforms: add KC705 2013-05-07 10:31:12 +02:00
Brandon Hamilton
3d0894465c mibuild: Add platform for Xilinx ML605 board 2013-05-06 14:21:56 +02:00
Sebastien Bourdeauducq
e4b0e8ed6d xilinx_ise: enable register balancing 2013-05-06 14:21:39 +02:00
Sebastien Bourdeauducq
85e06cc100 xilinx_ise: implement NoRetiming synthesis constraint 2013-04-25 14:57:45 +02:00
Sebastien Bourdeauducq
bd0ae6592e Add setup.py 2013-04-19 14:04:59 +02:00
Sebastien Bourdeauducq
6204bcfa10 README: fix quick intro 2013-04-19 14:00:46 +02:00
Sebastien Bourdeauducq
29eaf068f3 xilinx_ise: do not attempt to source settings file on Windows 2013-04-16 22:55:24 +02:00
Sebastien Bourdeauducq
31b1960188 xilinx_ise: add --no-source option to disable sourcing of ISE settings file 2013-04-16 22:39:35 +02:00
Werner Almesberger
59d64e92e8 mibuild: define memory card pins of the Milkymist One platorm 
This patch adds the memory card pins to the M1 platform definition in
mibuild.

I've tentatively named them "mmc". As far as I can tell, "MMC" is not
trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is
commonly used in the industry in a descriptive way to refer to this
sort of interface.

The original Verilog-based M1 calls the interface "mc", but since
several names have changed between milkymist and -ng, I thought I'd
use a more familiar name.

Usage example (clock signal divided by powers of two on the MMC TPs):
https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py

- Werner
 2013-04-12 09:51:57 +02:00
Sebastien Bourdeauducq
843f8a5bfc platforms: add Papilio Pro 2013-04-08 20:28:23 +02:00
Sebastien Bourdeauducq
715d332c3d crg: apply constraint to IO pins, not internal signals 2013-04-08 20:28:11 +02:00
Sebastien Bourdeauducq
8cf7c96a53 crg: use new platform.request 2013-03-26 23:08:35 +01:00
Sebastien Bourdeauducq
38e92eb92b altera_quartus: fix clock domain name 2013-03-26 23:05:46 +01:00
Sebastien Bourdeauducq
3b19dfc412 Support for platform info 2013-03-26 19:17:35 +01:00
Sebastien Bourdeauducq
74cc4d22cd generic_platform: remove obj in request + add lookup_request 2013-03-26 17:56:53 +01:00
Sebastien Bourdeauducq
003f1950cd xilinx_ise: fix clock domain names 2013-03-23 19:37:16 +01:00
Sebastien Bourdeauducq
797411c1a9 generic_platform: do not create clock domains during Verilog conversion 2013-03-18 18:44:58 +01:00
Sebastien Bourdeauducq
4bf3190244 MultiReg: remove idomain 2013-03-15 19:54:25 +01:00
Sebastien Bourdeauducq
6feb6e60b0 New clock_domain API 2013-03-15 18:46:11 +01:00
Sebastien Bourdeauducq
001beadb97 altera_quartus, de0nano: add copyright notices 2013-03-15 12:37:25 +01:00
Sebastien Bourdeauducq
f9e07b92a4 Added platform file for DE0 Nano (by Florent Kermarrec) 2013-03-15 11:41:38 +01:00
Sebastien Bourdeauducq
86d6f1d011 Added support for Altera Quartus (by Florent Kermarrec) 2013-03-15 11:32:12 +01:00
Sebastien Bourdeauducq
71c8172836 xilinx_ise/CRG_SE: reset inversion support 2013-03-15 11:31:36 +01:00
Sebastien Bourdeauducq
37d8029848 CRG: support reset inversion 2013-03-15 10:49:18 +01:00
Sebastien Bourdeauducq
24910173b7 CRG: use new Module API 2013-03-15 10:48:43 +01:00
Sebastien Bourdeauducq
c06a821452 generic_platform: implicit get_fragment 2013-03-12 16:14:13 +01:00
Sebastien Bourdeauducq
4d4d6c1f88 platforms/m1: add video mixer extension board 2013-03-05 23:03:01 +01:00
Sebastien Bourdeauducq
6a412f796e xilinx_ise: add lock cycle to bitgen 2013-03-01 11:29:40 +01:00
Sebastien Bourdeauducq
2b902fdcbd xilinx_ise: import Instance 2013-02-24 15:36:56 +01:00
Sebastien Bourdeauducq
d60ab1d215 Use new 'specials' API 2013-02-24 12:21:01 +01:00
Sebastien Bourdeauducq
56ae0f0714 xilinx_ise: disable SRL extraction on synchronizers 2013-02-23 19:43:12 +01:00
Sebastien Bourdeauducq
ef833422c7 generic_platform/get_verilog: pass additional args to verilog.convert 2013-02-23 19:42:29 +01:00
Sebastien Bourdeauducq
0321513726 corelogic -> genlib 2013-02-23 19:37:27 +01:00
Sebastien Bourdeauducq
44ae20d3c4 generic_platform: prefix subsignals 2013-02-20 18:27:04 +01:00