Sebastien Bourdeauducq
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b00e8fa826
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examples/fir: plot input and output signals
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2012-06-07 23:20:59 +02:00 |
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Sebastien Bourdeauducq
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081b658e2d
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Update copyright notices
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2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
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doc: more examples and comments
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2012-03-10 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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57a87b3316
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examples: FIR filter simulation
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2012-03-08 20:49:36 +01:00 |
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Sebastien Bourdeauducq
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f4adb0fe9c
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examples: remove outdated wb_intercon simulation
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2012-03-08 18:17:56 +01:00 |
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Sebastien Bourdeauducq
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ab800fa2ed
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bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
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Sebastien Bourdeauducq
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59a57e7a76
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examples: small cleanup
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2012-03-08 15:55:02 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
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sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
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9da512dbf5
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sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
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Sebastien Bourdeauducq
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22b3c11b93
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sim: clean startup/shutdown
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2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
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2012-02-16 18:34:32 +01:00 |
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Sebastien Bourdeauducq
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ef7aea0f31
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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
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2012-02-15 18:23:31 +01:00 |
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Sebastien Bourdeauducq
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91e279ee04
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bank/csrgen: use new bus API
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2012-02-15 16:42:17 +01:00 |
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Sebastien Bourdeauducq
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0493212124
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bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
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Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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3a2a0c4dd8
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bank: support registers larger than the bus word width
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2012-02-06 16:15:27 +01:00 |
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Sebastien Bourdeauducq
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f3ddfffc47
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bank: refactoring
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2012-02-06 13:55:50 +01:00 |
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Sebastien Bourdeauducq
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3143608e0a
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examples/wb_intercon: update to new APIs
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2012-01-28 23:18:21 +01:00 |
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Sebastien Bourdeauducq
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685b5eb08f
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fhdl: support memory read enable
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2012-01-27 21:39:23 +01:00 |
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Sebastien Bourdeauducq
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5405a83ff9
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fhdl: memories working
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2012-01-27 20:22:17 +01:00 |
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Sebastien Bourdeauducq
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076c171c7b
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Use meaningful class names
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2012-01-20 23:07:32 +01:00 |
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Sebastien Bourdeauducq
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a1043d11c0
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examples/corelogic_conv: use two dividers
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2012-01-16 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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bdde97f5fd
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New naming system beginning to work
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2012-01-16 18:42:55 +01:00 |
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Sebastien Bourdeauducq
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e6bfad498d
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actorlib/control: 'for' generator
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2012-01-15 22:08:33 +01:00 |
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Sebastien Bourdeauducq
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85491efc68
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wishbone_dma: convert to new endpoint API and fix some bugs
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2012-01-15 16:41:15 +01:00 |
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Sebastien Bourdeauducq
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a6e5f3e766
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flow: simplify actor fragment interface
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2012-01-10 15:54:51 +01:00 |
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Sebastien Bourdeauducq
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683e6b4a6c
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record: support aligned flattening
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2012-01-09 19:16:11 +01:00 |
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Sebastien Bourdeauducq
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b06e70d849
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corelogic: FSM
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2012-01-09 16:28:48 +01:00 |
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Sebastien Bourdeauducq
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89bf704b2b
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record: preserve order
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2012-01-09 15:14:42 +01:00 |
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Sebastien Bourdeauducq
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bdcaeb159b
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flow: draw network graph
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2012-01-09 14:21:54 +01:00 |
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Sebastien Bourdeauducq
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d2d55372d8
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Composer (WIP)
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2012-01-08 13:56:11 +01:00 |
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Sebastien Bourdeauducq
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0b195a244d
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flow: network
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2012-01-07 00:33:28 +01:00 |
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Sebastien Bourdeauducq
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588f1a259e
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flow: plumbing
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2012-01-06 17:24:05 +01:00 |
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Sebastien Bourdeauducq
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038992e7d2
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corelogic: record
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2012-01-06 11:20:44 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
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Sebastien Bourdeauducq
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1ce4fbdb98
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example: flow conversion
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2011-12-23 00:36:07 +01:00 |
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Sebastien Bourdeauducq
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af0a03b65f
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examples: remove old-style declarations
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2011-12-18 21:54:39 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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6f7a35e0a3
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examples: Wishbone interconnect test bench
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2011-12-13 14:10:56 +01:00 |
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Sebastien Bourdeauducq
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5034af3038
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Corelogic conversion example
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2011-12-08 21:25:05 +01:00 |
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Sebastien Bourdeauducq
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1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
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ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
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5acf2e169f
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Examples folder
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2011-12-04 23:39:48 +01:00 |