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litex
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454 Commits 40 Branches 14 Tags 51 MiB
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215 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ce82f188d0 framebuffer: fix deadlock 2012-07-07 00:12:34 +02:00
Sebastien Bourdeauducq 2b85624924 framebuffer: make simulation easier 2012-07-03 19:04:44 +02:00
Sebastien Bourdeauducq 210e473b5d framebuffer: fix computation of alignment bits 2012-07-03 18:14:39 +02:00
Sebastien Bourdeauducq 59289cfa3b framebuffer: indentation 2012-07-01 22:30:07 +02:00
Sebastien Bourdeauducq e2463da787 framebuffer: fake DMA for testing (WIP) 2012-07-01 21:46:11 +02:00
Sebastien Bourdeauducq fc458a51c9 framebuffer/vtg: fix dataflow control (inc. WA for Migen bug - FIXME) 2012-07-01 21:45:52 +02:00
Sebastien Bourdeauducq 7bf5461ac0 framebuffer: fix pixel split 2012-07-01 21:44:33 +02:00
Sebastien Bourdeauducq 0a29b74cce framebuffer: fix sync generation 2012-07-01 18:43:39 +02:00
Sebastien Bourdeauducq 8ba3118a83 framebuffer: register output of FIFO 2012-07-01 18:13:49 +02:00
Sebastien Bourdeauducq 309124711f framebuffer: video timing generator 2012-07-01 17:03:40 +02:00
Sebastien Bourdeauducq 16c6e4f4a7 framebuffer: FIFO 2012-07-01 15:22:57 +02:00
Sebastien Bourdeauducq acdd34e4ae framebuffer: VTG and FIFO skeleton 2012-06-29 17:09:16 +02:00
Sebastien Bourdeauducq ccbd5e8baf framebuffer: chop memory words 2012-06-29 16:11:05 +02:00
Sebastien Bourdeauducq 0f9e16a034 framebuffer: ala flow->actorlib 2012-06-24 19:15:19 +02:00
Sebastien Bourdeauducq 53fec3191c framebuffer: control.For -> misc.IntSequence 2012-06-22 15:01:25 +02:00
Sebastien Bourdeauducq ef13dc1eb1 framebuffer: address generator and DMA 2012-06-17 18:36:23 +02:00
Sebastien Bourdeauducq a52c3135c1 framebuffer: frame initiator 2012-06-17 17:22:02 +02:00
Sebastien Bourdeauducq 3a02524cc7 VGA framebuffer connections 2012-06-17 13:41:26 +02:00
Sebastien Bourdeauducq f6f42293d1 Clock frequency detection 2012-05-22 13:23:44 +02:00
Sebastien Bourdeauducq 5917048a37 minimac: add tx start register 2012-05-21 22:56:41 +02:00
Sebastien Bourdeauducq 94245517f2 Add timer 2012-05-21 19:46:04 +02:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 79124d822b Identifier 2012-05-17 01:41:41 +02:00
Sebastien Bourdeauducq 425c8b8e70 asmicon/multiplexer: fix read tag delay 2012-05-15 13:13:40 +02:00
Sebastien Bourdeauducq 19b1cc2529 Remove uses of pads, new constraints system 2012-04-02 19:22:17 +02:00
Sebastien Bourdeauducq d2c4afe66c asmicon: various fixes. Now produces convincing refresh/read sequences. 2012-04-01 23:24:24 +02:00
Sebastien Bourdeauducq ac7d89a4fe asmicon/bankmachine: fixes 2012-03-31 09:55:52 +02:00
Sebastien Bourdeauducq cd82f16806 asmicon/refresher: fix refresh sequence done signal 2012-03-30 16:26:50 +02:00
Sebastien Bourdeauducq c26efa28ca asmicon: multiplexer (untested) 2012-03-18 22:11:01 +01:00
Sebastien Bourdeauducq 0e00837f42 asmicon: move slot time to timing settings 2012-03-18 14:57:31 +01:00
Sebastien Bourdeauducq b1eb919ad2 asmicon: bank machine (untested) 2012-03-18 00:12:03 +01:00
Sebastien Bourdeauducq 7c377880fa asmicon: refresher (untested) 2012-03-15 20:29:26 +01:00
Sebastien Bourdeauducq e3ef121440 norflash: use new timeline API 2012-03-15 20:26:04 +01:00
Sebastien Bourdeauducq 7b14e0bd05 asmicon: skeleton 2012-03-14 18:26:05 +01:00
Sebastien Bourdeauducq baba267db6 ddrphy: request wrdata_en/rddata_en at the same time as the command 2012-02-24 15:14:58 +01:00
Sebastien Bourdeauducq 3179a27d14 dfii: set data mask 2012-02-23 22:00:51 +01:00
Sebastien Bourdeauducq 92ac69bae3 dfii: new design 2012-02-23 21:21:07 +01:00
Sebastien Bourdeauducq b4e041ecf1 s6ddrphy: write path OK in simulation 2012-02-20 23:55:20 +01:00
Sebastien Bourdeauducq f35cd4a85b Prepare for new DDR PHY 2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately. 2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq 5bc840b9c1 DFI injector (untested) 2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq c387ce7ce5 Map DDR PHY controls in CSR 2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY 
Doesn't do much for the moment, just to check synthesis/P&R.
 2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq cc5e4ae710 clkfx: remove 2012-02-16 19:30:00 +01:00
Sebastien Bourdeauducq 204452b0d3 m1crg: make clock feedback pin bidirectional 2012-02-16 18:35:44 +01:00
Sebastien Bourdeauducq f36a45edcb lm32: compatibility with the new instance API 2012-02-16 18:35:22 +01:00
Sebastien Bourdeauducq 72f9af9d90 Generate all clocks for the DDR PHY 2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq 859c9d8849 Use new bus API 2012-02-15 16:55:13 +01:00
Sebastien Bourdeauducq 506ffab11a uart: RX support 2012-02-07 14:12:23 +01:00
Sebastien Bourdeauducq 58f4f78d2c sram: fix sub-word write 2012-02-06 23:13:35 +01:00
Sebastien Bourdeauducq 5dc875de69 UART: use new bank API and event manager 2012-02-06 17:45:31 +01:00
Sebastien Bourdeauducq b5cb1083ab sram: fix WE signal 2012-02-03 10:38:17 +01:00
Sebastien Bourdeauducq 8a2646a549 Remove explicit bus names 2012-01-27 22:21:08 +01:00
Sebastien Bourdeauducq 28f00c3a9a Add on-chip SRAM 2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq 6fde54c5aa Use meaningful class names 2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq f8d5c27ef8 Wishbone: omit fixed LSBs 2012-01-13 17:28:58 +01:00
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq 3b640c45bb Use new syntax 2011-12-18 22:02:05 +01:00
Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq bb21f7584a 32-device, 8-bit CSR bus 2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq 85fbe07b94 clkfx module 2011-12-17 15:00:11 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq 738b45dcbd Support the new FHDL syntax 2011-12-16 21:30:22 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq b487e99bcf Initial import 2011-12-13 17:33:12 +01:00