516a1d3464
Update LM32 submodule
2013-08-14 19:16:44 +02:00
60f1585fef
use Migen s6ddrphy, generate sdram init_sequence in cif.py
2013-07-10 19:56:09 +02:00
4cd360e6e1
Mixxeo support
2013-07-04 19:19:39 +02:00
ce2f08844a
s6ddrphy: fix read latency
2013-06-11 16:02:34 +02:00
422c9a1db9
lasmi: reduce latencies by 1 cycle
2013-06-11 15:26:47 +02:00
91d7b656a9
Switch to LASMI, bug pandemonium
2013-06-11 14:18:16 +02:00
45cfdf41fc
New simplified flash layout + build flashable images for SoC and videomixer
2013-06-01 17:20:40 +02:00
679d13c99c
another attempt at fixing clock routing issues
2013-05-06 09:56:10 +02:00
4ff1175dcf
Use the Migen asynchronous FIFO
2013-04-25 19:43:26 +02:00
d64b64501a
minimac3: move psync
2013-04-25 18:36:45 +02:00
7133d9abb0
m1crg: reset VGA clock generator
2013-03-29 17:14:48 +01:00
b603eaf7d4
m1crg: allow up to 150MHz pixel clock
2013-03-28 20:45:42 +01:00
8fd092ca12
crg: support VGA pixel clock reprogramming
2013-03-28 19:07:17 +01:00
0c0140a8fb
m1crg: set CLKIN_PERIOD for vga_clock_gen
2013-03-17 20:16:58 +01:00
356416fcdc
lm32: update
2013-02-24 17:42:28 +01:00
70f4c74d46
m1crg: advance off-chip DDR clock phase
2013-02-24 17:41:56 +01:00
43343b131f
lm32: use submodule
2013-02-24 15:57:19 +01:00
7ad2f7081b
m1crg: fix signal names
2013-02-13 23:59:35 +01:00
5649e88a90
Use Mibuild
2013-02-11 18:23:06 +01:00
7a1e4cb66b
lm32: fix watchpoints
...
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-30 15:22:40 +01:00
a0ff666628
lm32: replace $clog2 with macro
...
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.
This commit can be reverted if the bug in XST is fixed.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:30:16 +01:00
d15d982904
lm32: split lm32_include.v
2012-11-14 14:25:15 +01:00
2ae17af75b
lm32: fix documentation style
...
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:09:21 +01:00
4bee685c54
lm32: remove unneeded parameter in lm32_dp_ram
...
addr_depth can be computed by addr_width.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:41 +01:00
10495e72d0
lm32: rename mem array in lm32_dp_ram
...
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
47baad4fe1
lm32: replace clogb2 by builtin $clog2
...
This function is fixed in ISE since version 14.1 (see AR #44586 ). If the
builtin function is used, the design can be simulated with Icarus Verilog.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
c86dd3cbef
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00
99bb705407
framebuffer: fix FIFO read clocking
2012-07-07 11:30:27 +02:00
16c6e4f4a7
framebuffer: FIFO
2012-07-01 15:22:57 +02:00
3a02524cc7
VGA framebuffer connections
2012-06-17 13:41:26 +02:00
22f7d1716e
Remove some boilerplate
2012-05-24 19:22:27 +02:00
4e18e45686
Add Ethernet MAC
2012-05-20 00:30:03 +02:00
7b14e0bd05
asmicon: skeleton
2012-03-14 18:26:05 +01:00
8d4a42887e
ddrphy: working on hardware, simulation a bit messed up
2012-02-24 15:44:51 +01:00
baba267db6
ddrphy: request wrdata_en/rddata_en at the same time as the command
2012-02-24 15:14:58 +01:00
17b2588321
ddrphy: reads OK, write data coming out 1/2 cycle too late
2012-02-24 15:05:52 +01:00
a363eb4a36
ddrphy: partly working
2012-02-24 13:54:10 +01:00
b3ca952a39
s6ddrphy: read path OK in simulation
2012-02-21 17:38:40 +01:00
b4e041ecf1
s6ddrphy: write path OK in simulation
2012-02-20 23:55:20 +01:00
ce51653381
s6ddrphy: generate DQ/DQS/DM OE
2012-02-20 16:13:56 +01:00
cbc3b7fa83
s6ddrphy: DQ/DQS/DM SERDES
2012-02-20 13:45:57 +01:00
4c1e18a9b5
s6ddrphy: clock, address and command
2012-02-19 20:49:56 +01:00
f35cd4a85b
Prepare for new DDR PHY
2012-02-19 18:43:42 +01:00
cdd58e023b
s6ddrphy: use single-ended DQS
2012-02-17 10:53:58 +01:00
72f9af9d90
Generate all clocks for the DDR PHY
2012-02-16 18:02:37 +01:00
1368b666df
s6ddrphy: prepare quilt
2012-02-14 15:52:39 +01:00
b6b1901bb8
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
6664af73d1
uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
bb21f7584a
32-device, 8-bit CSR bus
2011-12-17 15:54:42 +01:00
411e1af980
Proper reset generation
2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Michael Walle