Commit Graph

63 Commits

Author SHA1 Message Date
Florent Kermarec 603c2641bb new Ethernet MAC 2014-11-20 16:47:22 -08:00
Sebastien Bourdeauducq 20528c622a mor1kx: sync 2014-10-10 15:38:05 +08:00
Sebastien Bourdeauducq 503a2f00b5 mor1kx: sync 2014-09-12 16:00:32 +08:00
Sebastien Bourdeauducq 4d2623a87e mor1kx: sync 2014-08-09 14:32:57 +08:00
Sebastien Bourdeauducq 1a09eb7a19 mor1kx: sync 2014-08-03 15:57:55 +08:00
Sebastien Bourdeauducq 2cb7d73870 mor1kx: sync 2014-07-28 21:36:00 -06:00
Sebastien Bourdeauducq 6462ee7fe1 Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable. 2014-07-04 10:29:42 +02:00
Sebastien Bourdeauducq 1c08aeb21c Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
Sebastien Bourdeauducq 58e9792132 update submodule 2013-12-06 00:07:05 +01:00
Sebastien Bourdeauducq 96600ad9d7 set LM32 reset address 2013-11-25 12:09:16 +01:00
Sebastien Bourdeauducq d7a4d8b66e use git commit id as version 2013-11-09 16:38:44 +01:00
Sebastien Bourdeauducq e6e04a2e3a framebuffer: prepare for DVI out 2013-09-17 18:15:22 +02:00
Sebastien Bourdeauducq 516a1d3464 Update LM32 submodule 2013-08-14 19:16:44 +02:00
Florent Kermarrec 60f1585fef use Migen s6ddrphy, generate sdram init_sequence in cif.py 2013-07-10 19:56:09 +02:00
Sebastien Bourdeauducq 4cd360e6e1 Mixxeo support 2013-07-04 19:19:39 +02:00
Sebastien Bourdeauducq ce2f08844a s6ddrphy: fix read latency 2013-06-11 16:02:34 +02:00
Sebastien Bourdeauducq 422c9a1db9 lasmi: reduce latencies by 1 cycle 2013-06-11 15:26:47 +02:00
Sebastien Bourdeauducq 91d7b656a9 Switch to LASMI, bug pandemonium 2013-06-11 14:18:16 +02:00
Sebastien Bourdeauducq 45cfdf41fc New simplified flash layout + build flashable images for SoC and videomixer 2013-06-01 17:20:40 +02:00
Sebastien Bourdeauducq 679d13c99c another attempt at fixing clock routing issues 2013-05-06 09:56:10 +02:00
Sebastien Bourdeauducq 4ff1175dcf Use the Migen asynchronous FIFO 2013-04-25 19:43:26 +02:00
Sebastien Bourdeauducq d64b64501a minimac3: move psync 2013-04-25 18:36:45 +02:00
Sebastien Bourdeauducq 7133d9abb0 m1crg: reset VGA clock generator 2013-03-29 17:14:48 +01:00
Sebastien Bourdeauducq b603eaf7d4 m1crg: allow up to 150MHz pixel clock 2013-03-28 20:45:42 +01:00
Sebastien Bourdeauducq 8fd092ca12 crg: support VGA pixel clock reprogramming 2013-03-28 19:07:17 +01:00
Sebastien Bourdeauducq 0c0140a8fb m1crg: set CLKIN_PERIOD for vga_clock_gen 2013-03-17 20:16:58 +01:00
Sebastien Bourdeauducq 356416fcdc lm32: update 2013-02-24 17:42:28 +01:00
Sebastien Bourdeauducq 70f4c74d46 m1crg: advance off-chip DDR clock phase 2013-02-24 17:41:56 +01:00
Sebastien Bourdeauducq 43343b131f lm32: use submodule 2013-02-24 15:57:19 +01:00
Sebastien Bourdeauducq 7ad2f7081b m1crg: fix signal names 2013-02-13 23:59:35 +01:00
Sebastien Bourdeauducq 5649e88a90 Use Mibuild 2013-02-11 18:23:06 +01:00
Michael Walle 7a1e4cb66b lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-30 15:22:40 +01:00
Michael Walle a0ff666628 lm32: replace $clog2 with macro
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.

This commit can be reverted if the bug in XST is fixed.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:30:16 +01:00
Sebastien Bourdeauducq d15d982904 lm32: split lm32_include.v 2012-11-14 14:25:15 +01:00
Michael Walle 2ae17af75b lm32: fix documentation style
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:09:21 +01:00
Michael Walle 4bee685c54 lm32: remove unneeded parameter in lm32_dp_ram
addr_depth can be computed by addr_width.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:41 +01:00
Michael Walle 10495e72d0 lm32: rename mem array in lm32_dp_ram
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
Michael Walle 47baad4fe1 lm32: replace clogb2 by builtin $clog2
This function is fixed in ISE since version 14.1 (see AR #44586). If the
builtin function is used, the design can be simulated with Icarus Verilog.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 99bb705407 framebuffer: fix FIFO read clocking 2012-07-07 11:30:27 +02:00
Sebastien Bourdeauducq 16c6e4f4a7 framebuffer: FIFO 2012-07-01 15:22:57 +02:00
Sebastien Bourdeauducq 3a02524cc7 VGA framebuffer connections 2012-06-17 13:41:26 +02:00
Sebastien Bourdeauducq 22f7d1716e Remove some boilerplate 2012-05-24 19:22:27 +02:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 7b14e0bd05 asmicon: skeleton 2012-03-14 18:26:05 +01:00
Sebastien Bourdeauducq 8d4a42887e ddrphy: working on hardware, simulation a bit messed up 2012-02-24 15:44:51 +01:00
Sebastien Bourdeauducq baba267db6 ddrphy: request wrdata_en/rddata_en at the same time as the command 2012-02-24 15:14:58 +01:00
Sebastien Bourdeauducq 17b2588321 ddrphy: reads OK, write data coming out 1/2 cycle too late 2012-02-24 15:05:52 +01:00
Sebastien Bourdeauducq a363eb4a36 ddrphy: partly working 2012-02-24 13:54:10 +01:00
Sebastien Bourdeauducq b3ca952a39 s6ddrphy: read path OK in simulation 2012-02-21 17:38:40 +01:00