a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
ea613cd8ee
litesata: update build core target generation
2015-04-09 00:00:25 +02:00
03aa972bb6
lite*: finish ModuleTransformer adaptations (need to be tested on board)
2015-04-08 23:27:22 +02:00
3a2b677f85
soc,cpuif: support user defined constants
2015-04-09 00:34:36 +08:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
8ce683964a
mibuild/tools/write_to_file: use context manager
2015-04-08 19:41:54 +08:00
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
8b41ab3a5f
make: add target in build names
2015-04-06 23:53:04 +08:00
176b9240a9
soc: use new ModuleTransformer API
2015-04-06 23:52:34 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
66f8dcbfaf
lite*: adapt to new ModuleTransformer semantics
...
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
aac953dd90
vivado: support phys_opt
2015-04-04 19:00:22 +08:00
9506f69390
vivado: add support for pre_synthesis_commands
2015-04-04 19:00:01 +08:00
4522956f11
vivado: make _build_files() a method and rename
2015-04-04 18:59:50 +08:00
1d1189506a
mibuild: support multiple specifications of include file and sources
2015-04-04 18:58:02 +08:00
2583e975f0
soc/cpuif: fix CSR base generation for memories (name is already fullname)
2015-04-03 13:57:37 +02:00
c9c11e7aa8
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
2015-04-03 12:45:32 +02:00
85b3cced22
use str.format
2015-04-03 17:43:46 +08:00
c7361f1cdf
software/common.mak: fix alignment in quiet output
2015-04-03 17:43:29 +08:00
0db6e1d624
soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube)
2015-04-03 11:14:28 +02:00
875abdeb8d
make.py: use os.path.join
2015-04-03 16:00:07 +08:00
73d3b8487c
crt0-or1k: clean up indentation
2015-04-03 13:23:28 +08:00
357c807eb1
Merge branch 'master' of github.com:m-labs/migen
2015-04-02 20:23:12 +08:00
ce429841d5
kc705: fix typo in platform file (LPC definition)
2015-04-02 20:21:20 +08:00
b437dc3185
remove use of _r prefix on CSRs
2015-04-02 12:18:43 +02:00
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
d67f24ddc7
migen/bank/description: remove support of _r prefix in CSRs
2015-04-02 12:13:22 +02:00
696819cc7f
move gpio from cpu.peripherals to com
2015-04-02 17:17:33 +08:00
63f14f3f30
libbase: implement flush_l2_cache for or1k
2015-04-02 16:47:03 +08:00
382ed013af
minor cleanups
2015-04-02 14:40:29 +08:00
bbdbf87599
Merge branch 'master' of github.com:m-labs/misoc
2015-04-02 10:14:24 +08:00
60124be293
adapt LiteSATA to new SoC
2015-04-01 22:52:19 +02:00
dcdf5df4de
adapt LiteEth to new SoC
2015-04-01 22:50:29 +02:00
f65c0a3c95
adapt LiteScope to new SoC
2015-04-01 22:46:24 +02:00
2d23ab7a85
soc/sdram: fix do_finalize
2015-04-01 22:38:04 +02:00
2900429e65
soc: use set
2015-04-02 00:14:56 +08:00
369086a178
soc: simplify integrated memory parameters
2015-04-02 00:09:38 +08:00
273242b399
soc/sdram: minor cleanup
2015-04-01 23:41:55 +08:00
6e2a662dd7
litesata: adapt to new SoC API
2015-04-01 17:37:53 +08:00
9599eb6fae
soc: remove cpu_boot_file argument
2015-04-01 17:32:45 +08:00
fb86445d14
soc: remove cpu_or_bridge and with_cpu arguments
2015-04-01 17:29:51 +08:00
a148af97ba
soc: retrieve csr and memory regions using methods
2015-04-01 16:49:32 +08:00
8b19a11cd7
soc: use add_wb_master function
2015-04-01 15:56:54 +08:00
2a1112b912
soc: simplify/fix csr busword
2015-04-01 15:48:56 +08:00
04f29e97e2
soc: remove unnecessary imports
2015-04-01 15:15:09 +08:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens
Yann Sionneau