Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,857 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

4857 Commits

Author SHA1 Message Date
Florent Kermarrec 2638393b53 soc_zynq: fix indent 2019-09-05 15:59:35 +02:00
Florent Kermarrec 9051cf97e4 soc_zynq: fix typo 2019-09-05 15:55:18 +02:00
Florent Kermarrec 67a09aef05 soc/interconnect/stream: add Monitor module 
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
 2019-09-05 11:54:14 +02:00
enjoy-digital 6f150a5626
Merge pull request #254 from mithro/crc-smaller 
Add @xobs' smaller CRC version
 2019-09-03 07:23:32 +02:00
Tim 'mithro' Ansell 2a41f0d2a4 Use `SMALL_CRC` to enable smaller CRC versions. 
@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
 2019-09-02 14:48:30 -07:00
Tim 'mithro' Ansell 083337441a Remove extra whitespace. 2019-09-02 14:47:20 -07:00
Sean Cross c0e723868e libbase: crc16: commit smaller version of crc16 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Sean Cross a59d0efca0 libbase: crc32: add smaller version 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Tim Ansell 27c334d440
Merge pull request #252 from mithro/only-change-on-contents 
Only write file if contents will change.
 2019-09-02 14:42:22 -07:00
Tim 'mithro' Ansell 3ff6a18a45 Only write file if contents will change. 2019-09-02 14:26:41 -07:00
Florent Kermarrec a2938a7ae7 soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" 2019-08-31 18:34:08 +02:00
enjoy-digital 19d3acfc71
Merge pull request #251 from micro-FPGA/master 
atlantic JTAG UART working module
 2019-08-31 18:33:27 +02:00
Antti Lukats fb00ee85a2 Create atlantic.py 
atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
 2019-08-30 09:35:10 +02:00
Florent Kermarrec 41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec b845755995 gen/fhdl/verilog: allow single element verilog inline attribute 2019-08-28 05:24:11 +02:00
Florent Kermarrec 5a7b4c3406 targets/nexys_video: generate clk100 2019-08-27 14:06:13 +02:00
Florent Kermarrec c179741cf3 software/bios: switch to standard CRLF 
Avoid setting terminal to "implicit CR in every LF" mode.
 2019-08-27 09:45:44 +02:00
Florent Kermarrec 0328ba7d6c tools/litex_term: add automatic check to see if we need to insert LF or not 2019-08-26 18:17:43 +02:00
Florent Kermarrec ffebd2076c bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) 2019-08-26 17:15:01 +02:00
Florent Kermarrec 4842bdcf08 tools/litex_term: add sdl_payload_length 2019-08-26 12:10:11 +02:00
Florent Kermarrec 3e30c64842 litex_setup: add litex-boards 2019-08-26 09:28:58 +02:00
enjoy-digital d79cd87dd6
Merge pull request #246 from gsomlo/gls-native-rv64 
software: use native toolchain for same host, target architectures
 2019-08-23 21:36:51 +02:00
Gabriel L. Somlo 6d844a038a software: use native toolchain for same host, target architectures 
LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-08-23 09:04:55 -04:00
enjoy-digital d36f1fb7d2
Merge pull request #244 from atommann/master 
changing http to https
 2019-08-17 11:54:39 +02:00
atommann a45dbee54f changing http to https 2019-08-17 16:02:10 +08:00
Antti Lukats 92e5b4b2cd
Merge pull request #2 from enjoy-digital/master 
update with hyperram and other changes
 2019-08-16 14:36:59 +02:00
Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 2019-08-16 14:04:58 +02:00
Antti Lukats f47e4978f2 libero enable enhanced constraints 
Libero 12.0 does not support any more classic constraint flow
 2019-08-16 10:31:53 +02:00
Antti Lukats d1502d4195 soc/cores: add initial simple hyperram core 2019-08-16 09:48:17 +02:00
Florent Kermarrec 6e6fe83af3 build/altera/quartus: add add_ip method to use Quartus QSYS files 
platform.add_ip("my_ip.qsys")
 2019-08-15 13:45:29 +02:00
Florent Kermarrec 2899928aba cpu_interface: add json csr map export, simplify csv csr map export using json 2019-08-15 09:27:33 +02:00
Florent Kermarrec 9d4b7cd515 bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) 2019-08-14 19:09:58 +02:00
Florent Kermarrec 0cd4e45f48 build/xilinx/vivado: use "" for strings 2019-08-14 19:03:10 +02:00
Florent Kermarrec 8d161a47cf build/xilinx/vivado: remove with_phys_opt 2019-08-14 19:02:01 +02:00
enjoy-digital f6638ded13
Merge pull request #243 from sergachev/master 
build/xilinx/vivado: improve directive support
 2019-08-14 18:58:15 +02:00
enjoy-digital ccc2cbd9d4
Merge pull request #241 from railnova/zynq 
[fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat
 2019-08-14 18:55:34 +02:00
Ilia Sergachev 861eea8a07 build/xilinx/vivado: improve directive support 2019-08-14 17:49:13 +02:00
chmousset db4c609a33 [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat 2019-08-14 11:30:39 +02:00
Florent Kermarrec 6d5fddc160 cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) 2019-08-14 07:35:45 +02:00
enjoy-digital 383c05e239
Merge pull request #240 from danielkucera/patch-1 
more understandable error when missing a memory
 2019-08-13 10:34:50 +02:00
Daniel Kucera a5eaf172c5
more understandable error when missing a memory 2019-08-13 10:14:16 +02:00
atommann 1d957d7a31
Update .gitmodules 
http to https
 2019-08-12 22:20:34 +08:00
enjoy-digital 2b815f7096
Merge pull request #235 from gsomlo/gls-trellis-yosys-opt 
build/lattice/trellis: use additional yosys optimization flags
 2019-08-10 15:33:05 +02:00
Gabriel L. Somlo 6c298cb708 build/lattice/trellis: use abc9 techmapping pass with yosys 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-08-09 09:12:22 -04:00
Florent Kermarrec 31bfb54667 software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys 2019-08-09 13:26:31 +02:00
Florent Kermarrec e670cb9176 cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus 2019-08-09 12:33:10 +02:00
Florent Kermarrec 6d94c07d70 software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle 2019-08-09 10:33:42 +02:00
Florent Kermarrec 0c287b11ba cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap 2019-08-09 09:27:32 +02:00
Florent Kermarrec 82cd557c24 software/bios: add Ethernet PHY MDIO read/write/dump commands 2019-08-09 09:26:41 +02:00
Florent Kermarrec 0ba9ab92b4 altera/common: fix AsyncResetSynchronizer polarity and simplify 2019-08-08 16:19:22 +02:00