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9482 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou 50cf037bef build/xilinx/f4pga: adding edalize backend support 2022-10-29 09:14:49 +02:00
Gwenhael Goavec-Merou 949f262ce9 build/xilinx/f4pga: XDC -> xdc 2022-10-29 09:14:05 +02:00
Gwenhael Goavec-Merou 79cc3698b8 build/generic_toolchain, build/lattice/icestorm: tool_options is now a dict {key, value} (with value can be a dict) => edaflow compat 2022-10-29 09:12:51 +02:00
Gwenhael Goavec-Merou ab6bb331fd build/generic_toolchain: space before = 2022-10-29 09:08:19 +02:00
Florent Kermarrec 2086cced22 soc/interconnect/csr_eventmanager: Also switch to new Reduce. 2022-10-28 19:38:45 +02:00
Florent Kermarrec 2829ca93f7 litex/gen: Move LiteXModule to gen/fhdl/module.py. 2022-10-28 19:38:24 +02:00
Florent Kermarrec e3e99c527c soc/cores/interconnect: Switch most of the cores to new Reduce. 2022-10-28 19:31:33 +02:00
Florent Kermarrec a10b1fd1e6 gen/common/Reduce: Add ADD support. 2022-10-28 19:13:27 +02:00
Florent Kermarrec 5106fd43fc gen/common: Add Reduction function (To avoid using Python's reduction directly which is messy/confusing). 2022-10-28 15:13:17 +02:00
Florent Kermarrec 13448b8260 soc/SoCBusHandler: Integrate interconnect code since avoid duplication and simplify reuse. 
Also extends supported data_widths.

A simple custom interconnect can now be created with code like this:

# Create 2 AXI Masters / 2 AXI Slaves.
axi_m_0 = axi.AXIInterface(data_width=32,  address_width=32)
axi_m_1 = axi.AXIInterface(data_width=64,  address_width=32)
axi_s_0 = axi.AXIInterface(data_width=512, address_width=32)
axi_s_1 = axi.AXIInterface(data_width=512, address_width=32)

axi_s_0_region = SoCRegion(origin=0x00000000, size=0x10000000)
axi_s_1_region = SoCRegion(origin=0x10000000, size=0x10000000)

# Create Bus Handler .
self.custom_bus = SoCBusHandler(
    name                  = "SoCCustomBusHandler",
    standard              = "axi",
    data_width            = 512,
    address_width         = 32,
    bursting              = True,
    interconnect          = "crossbar",
    interconnect_register = True,
)

# Add AXI Buses.
self.custom_bus.add_master(master=axi_m_0)
self.custom_bus.add_master(master=axi_m_1)
self.custom_bus.add_slave(slave=axi_s_0, region=axi_s_0_region)
self.custom_bus.add_slave(slave=axi_s_0, region=axi_s_1_region)

# Finalize.
self.custom_bus.finalize()
print(self.custom_bus)
 2022-10-28 12:47:38 +02:00
Florent Kermarrec 3603e90ed8 integration/soc/SoC: Add collection of CSRs described in Main Module (ie Top-Level). 
CSRs added to the Main Module were silently ignored. These are now collected and automatically
added to a "main" Sub-Module.

This feature is useful to quickly create/add CSRs in the design when debugging, ex:

# Adds a "debug" CSR to a SoC and connect register to pads:
self.debug = CSRStorage()
self.comb += pads.debug.eq(self.debug.storage).
 2022-10-28 10:04:12 +02:00
Florent Kermarrec 1f2d4f017a integration/soc: Switch to LiteXModule and from self.submodules/self.clock_domains to self. 2022-10-27 16:04:17 +02:00
Florent Kermarrec f8702d744f gen/common/LiteXModule: Also inherit from AutoDoc. 2022-10-27 15:52:21 +02:00
Florent Kermarrec a71fd1d31b gen/common: Introduce LiteXModule class to simplify Modules creation and avoid common mistakes. 
LiteXModule can be used as a remplacement of Migen's Module and in this initial version:
- Automatically inherit from AutoCSR (Forgeting to inherit from AutoCSR on a Module was a common mistake).
- Simplify design creation with:
  - m.module_x  = .. equivalent of Migen's m.submodules.module_x = ..
  - m.special_x = .. equivalent of Migen's m.specials.special_x  = ..
  - m.cd_x      = .. equivalent of Migen's m.clock_domains.cd_x  = ..
  - m += module_x  equivalent of Migen's m.submodules += module_x.
  - m += special_x equivalent of Migen's m.specials += special_x.
  - m += cd_x  equivalent of Migen's m.clock_domains += cd_x.
-> Forgeting to attach a correctly a Sub-module/Special was a very common mistake and having to use
m.submodules., m.specials., m.clock_domains. was not natural.
 2022-10-27 15:29:50 +02:00
Tim 'mithro' Ansell e570b612b2
Merge pull request #1470 from shenki/update-microwatt 
Update Microwatt
 2022-10-26 21:10:32 -07:00
Joel Stanley 4ccf9f487d microwatt: Fix irq variant 
The vhd2v conversion missed some things that are only run when building
the irq variant.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-10-26 17:27:15 +10:30
Joel Stanley d45d3532fe microwatt: Update to latest 
Add the new source files and bump the revision used.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-10-26 17:03:47 +10:30
Joel Stanley f95cf6ab2d vhd2v: Fix mixed langauge support 
Moving to the new vhdl to verilog code broke the Vivado support where
there's no conversion required.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-10-26 16:29:53 +10:30
Florent Kermarrec 611b84ccee build/sim/Verilator: Skip .hex in sources. 
Useful to use platform.add_source to add/copy .hex files.
 2022-10-24 18:21:10 +02:00
Florent Kermarrec af445e93dd build/vendor/common: Minor style cleanup. 2022-10-24 09:33:35 +02:00
Florent Kermarrec 88d89773ef interconnect/csr: Sort by DUID even with sort=False (for retro-compatibility). 2022-10-22 09:21:37 +02:00
Florent Kermarrec 50acdf73a4 interconnect/csr_bus: Add missing part of the previous fix... 2022-10-21 23:06:25 +02:00
Florent Kermarrec 76d3a77cf3 interconnect/csr_bus: Fix build with custom get_csrs/get_constants from cores. 2022-10-21 22:01:34 +02:00
Florent Kermarrec d30f780a87 fhdl/verilog: Switch tab to 4 spaces. 2022-10-21 19:49:04 +02:00
Florent Kermarrec 84c3e9c50e fhdl/verilog: Make tab configurable. 2022-10-21 19:47:28 +02:00
Florent Kermarrec 1f58ce3c31 gen/fhdl/verilog: Improve _print_signal to align signals definition. 2022-10-21 19:39:02 +02:00
Florent Kermarrec b6e672a060 fhdl/verilog: Move inline verilog attribute to previous line to improve readability of the generated verilog. 2022-10-21 19:19:28 +02:00
Florent Kermarrec 096f2184e6 soc/interconnect/csr: Replace level with sort and fix targets compilation. 2022-10-21 18:54:12 +02:00
enjoy-digital 14b2829a5f
Merge pull request #1467 from enjoy-digital/csr_mapping 
Add optional support for fixed CSR mapping.
 2022-10-21 18:36:26 +02:00
Florent Kermarrec a60a51c52f interconnect/csr: Only sort gathered items at Module level. 2022-10-21 16:04:23 +02:00
Florent Kermarrec a57f0640cc soc/interconnect/csr: Add optional support fixed CSR mapping. 
By default, location is still automatically determined but it's now possible to
specific locations:

The following module:

class MyModule(Module, AutoCSR):
    def __init__(self):
        self.csr0 = CSRStorage()
        self.csr1 = CSRStorage(n=0)
        self.csr2 = CSRStorage(n=2)

built on a SoC with 32-bit CSR data-width will have the following CSR mapping:
- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2
 2022-10-21 14:47:59 +02:00
Florent Kermarrec 804a1a5b26 soc/add_uart: Improve error message for unsupported UART. 2022-10-21 09:03:25 +02:00
Florent Kermarrec 73d70cf594 build/sim/platform: Remove add_csr calls no longer required. 2022-10-21 08:43:51 +02:00
enjoy-digital 525bbd19a9
Merge pull request #1465 from mohamedElbouazzati/cv32e41p_interrupts 
Fix IRQS handling for cv32e41p
 2022-10-20 16:00:39 +02:00
mohamedElbouazzati 85e9881f45 Fix IRQS for cv32e41p 2022-10-19 17:48:36 +02:00
Florent Kermarrec da8d3d10aa tools/litex_read_verilog: Add proc step before exporting to .json since now seems to be required for some verilog designs. 2022-10-19 15:29:00 +02:00
Florent Kermarrec 89670e5938 soc/cores/spi: Add SPIBone import. 
Allow importing SPIBone with:
from litex.soc.cores.spi import SPIBone
 2022-10-19 15:22:04 +02:00
Florent Kermarrec 519b411954 core/spi/spi_bone: Update header. 2022-10-19 11:40:51 +02:00
Florent Kermarrec 4e8e97a22a cores/spi/spi_bone: Cosmetic cleanups on FSM (rename states). 2022-10-19 11:40:23 +02:00
Florent Kermarrec bdfb032be9 cores/spi/spi_bone: More cosmetic cleanups. 2022-10-19 11:29:03 +02:00
Florent Kermarrec 0b05abb44f cores/spi/spi_bone: Rename self.wishbone to self.bus/bus. 2022-10-19 11:10:21 +02:00
Florent Kermarrec b6b3ab4f11 cores/spi/spi_bone: Move Clk edges detection and rename signals (rising -> posedge, falling -> negedge). 2022-10-19 11:02:43 +02:00
Florent Kermarrec 710a1958a4 cores/spi/spi_bone: Separate SPI IOs handling from Signals. 2022-10-19 10:55:44 +02:00
Florent Kermarrec 2a15ab554a cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases. 2022-10-19 10:53:26 +02:00
Florent Kermarrec eabdc0b7e9 cores/spi/spi_bone: Cosmetic cleanup pass (and remove unreachable ValueErrors). 2022-10-19 10:48:13 +02:00
Florent Kermarrec 296fc7add0 cores/spi/spi_bone: Spi -> SPI and rename SpiWishboneBridge to SPIBone. 2022-10-19 10:37:11 +02:00
Florent Kermarrec b6069a4d62 soc/cores/spi/spi_master: Remove SPISlave. 2022-10-18 18:22:33 +02:00
Sean Cross 9f52ed1207 soc/cores/spi: Integrate SPIWishboneBridge from https://github.com/xobs/spibone. 
"The ability to bridge Wishbone is an incredibly powerful one. However, the various bridges can be rather heavy in terms of resource usage. This presents a simple bridge that operates over SPI."
 2022-10-18 18:20:50 +02:00
Florent Kermarrec f5c9425e14 soc/cores/spi: Create spi directory and split spi.py in spi_master/spi_slave. 
__init__.py provide imports compatibility.
 2022-10-18 18:16:35 +02:00
Florent Kermarrec f7e05b1953 interconnect/axi: Add 8-bit/16-bit data-widths. 2022-10-18 14:15:08 +02:00