Commit Graph

1287 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 91ab3f0d01 remove genlib.misc.optree (use reduce instead) 2015-09-10 13:56:56 -07:00
Yves Delley 1dcd2ac1c0 fixed bug in value_bits_sign of mul operatiors 2015-09-10 10:53:26 -07:00
Sebastien Bourdeauducq 86f34e82c3 mibuild -> migen.build 2015-09-10 10:53:15 -07:00
Sebastien Bourdeauducq f1dc008d32 Simulator will be rewritten 2015-09-05 15:07:00 -06:00
Sebastien Bourdeauducq dec2e23fc7 Remove code that will be into MiSoC or other packages. 2015-09-05 15:06:04 -06:00
Florent Kermarrec 5253b0c06e migen/actorlib/packet: fix source.error in Depacketizer 2015-08-19 01:12:07 +02:00
Florent Kermarrec 9210df9e9f mibuild/xilinx/ise: update synthesis with yosis 2015-08-19 01:12:05 +02:00
Florent Kermarrec 646667213e migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active) 2015-08-09 19:54:38 +02:00
Ryan Verner 9c902bcd86 Port fpgalink_programmer to use newer fl library.
* See change in 2074e51a33
2015-08-04 21:42:29 +08:00
Sebastien Bourdeauducq df2306ab88 try to use the new anaconda-client 2015-07-31 13:46:28 +08:00
Sebastien Bourdeauducq abbb76ce84 ise: do not use LCK_cycle:6 by default 2015-07-29 11:09:42 +08:00
Robert Jordens a11d065546 pipistrello: fix cts/rts
* use the same perspective as for tx/rx (flipped w.r.t. the ftdi chip)
* add pullups in case target or host attempt to use handshaking
2015-07-27 21:46:24 -06:00
Sebastien Bourdeauducq b7784fcbd7 platforms/kc705: add GPIO SMA 2015-07-28 00:19:39 +08:00
Sebastien Bourdeauducq f32f9be17a resetless -> reset_less 2015-07-27 11:46:11 +08:00
Sebastien Bourdeauducq cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains 2015-07-27 01:51:52 +08:00
Sebastien Bourdeauducq 5a535ef347 Revert "migen/actorlib/fifo: add FIFO wrapper function"
This reverts commit d0a19c4be8.
2015-07-24 19:25:36 +08:00
Florent Kermarrec d0a19c4be8 migen/actorlib/fifo: add FIFO wrapper function
Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
2015-07-24 13:02:54 +02:00
Florent Kermarrec 1f1ff5a5e9 migen/fhdl/tools: fix rename_clock_domain when new == old
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
Florent Kermarrec 493f424ebd Merge branch 'master' of https://github.com/m-labs/migen 2015-07-22 21:46:23 +02:00
Florent Kermarrec 5713ae381a actorlib/packet/Depacketizer: manage layouts without error signal 2015-07-22 21:43:21 +02:00
numato 09b33346be Removed drive strength constraints on VGA/Audio signals 2015-07-14 23:00:26 +02:00
Robert Jordens 6468fa3db4 xilinx: ensure we chdir() back after build 2015-07-14 12:53:43 -06:00
Sebastien Bourdeauducq 52bdc29528 mimasv2: style, consistency with other boards 2015-07-14 19:56:00 +02:00
numato e56d80c7a0 Adding support for Numato Lab Mimas V2 platform 2015-07-14 19:42:51 +02:00
Sebastien Bourdeauducq ea8ffd8e80 platforms/kc705: style 2015-07-14 19:42:44 +02:00
Robert Jordens 8d6aa82082 mibuild/openocd.py: add support
Tested with pipistrello and kc705. Needs patches from
https://github.com/jordens/openocd/tree/bscan_spi waiting
to be merged in the openocd queue.
2015-07-07 21:01:31 -06:00
Sebastien Bourdeauducq 73ea404380 Merge branch 'master' of https://github.com/m-labs/migen 2015-07-05 10:53:32 +02:00
Tim 'mithro' Ansell 1d1f8510d3 Allow using non-milkymist cables with UrJTAG. 2015-07-05 10:53:09 +02:00
Tim 'mithro' Ansell 0df9c16e69 mibuild: Adding error checking around xsvf generation 2015-07-02 16:51:03 +02:00
Tim 'mithro' Ansell 8daf5e32c1 Adding support for programming with FPGALink
Steps for getting it set up.

 * Get libfpgalink dependencies
   sudo apt-get install \
      build-essential libreadline-dev libusb-1.0-0-dev python-yaml

 * Build libfpgalink
   wget -qO- http://tiny.cc/msbil | tar zxf -
   cd makestuff; ./scripts/msget.sh makestuff/common
   cd libs; ../scripts/msget.sh libfpgalink
   cd libfpgalink; make deps

 * Convert libfpgalink to python3
   wget -O - http://www.swaton.ukfsn.org/bin/2to3.tar.gz | tar zxf -
   cd examples/python
   cp fpgalink2.py fpgalink3.py
   ../../2to3/2to3 fpgalink3.py | patch fpgalink3.py

 * Set your path's correctly.

   export LD_LIBRARY_PATH=$(pwd)/libfpgalink/lin.x64/rel:$LD_LIBRARY_PATH
   export PYTHON_PATH=$(pwd)/libfpgalink/examples/python:$PYTHON_PATH
2015-07-02 16:44:39 +02:00
Tim 'mithro' Ansell 055f7d51fc mibuild/xilinx: Adding programming with the Digilent Adept tools 2015-07-02 16:03:44 +02:00
Florent Kermarrec 7afa3d61d9 mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation
Fix DDROutput implementation on spartan6 (tested with LiteETH's GMII phy)
2015-07-02 09:42:12 +02:00
Yann Sionneau 4509265c70 travis: use use-local for conda install
http://conda.pydata.org/docs/build_tutorials/pkgs.html
2015-06-30 00:42:56 +02:00
William D. Jones 445f0f5d40 Remove self.programmer references in Mercury, as mercury programmer is not implemented. 2015-06-28 18:06:50 +02:00
William D. Jones 3ea7ef81a9 Add Mercury dev board to mibuild (http://www.micro-nova.com/mercury/) 2015-06-28 16:30:41 +02:00
Sébastien Bourdeauducq f03c2325d9 Merge pull request #21 from psmears/patch-1
Minor improvements to wording
2015-06-24 10:46:58 +00:00
Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
Florent Kermarrec 71627cf9f0 bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant) 2015-06-19 08:37:16 +02:00
Florent Kermarrec 7d8f4d1009 mibuild/xilinx/ise: fix source and set source to False by default on Windows (tools supposed to be in the PATH) 2015-06-19 00:52:39 +02:00
Florent Kermarrec 743a5f6ea9 mibuild/xilinx/ise: simplify default_ise_path 2015-06-19 00:40:05 +02:00
William D. Jones 6370acd968 Xilinx Platforms now use cmd.exe on Windows instead of bash to run scripts
(remove MSYS dependency)
2015-06-19 00:30:22 +02:00
psmears d435f30fa3 Minor improvements to wording 2015-06-18 12:26:22 +01:00
Florent Kermarrec f8b1152b98 wishbone: add Cache (from WB2LASMI) 2015-06-17 15:31:49 +02:00
Yann Sionneau 6e876c63ad pipistrello: fix FPGA speed grade 2015-06-14 23:19:27 +02:00
Florent Kermarrec 33b536e505 migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter) 2015-06-02 19:29:38 +02:00
Florent Kermarrec 79624ce849 migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq fd16b66bdf genlib/cdc: add BusSynchronizer 2015-06-02 17:40:42 +08:00
Sebastien Bourdeauducq 57102ec160 setup.py: valid version number (fixes issue #12) 2015-05-28 15:43:31 +08:00
Florent Kermarrec a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00
Florent Kermarrec 9cabcf14e9 migen/genlib/record: add leave_out parameter to connect
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00