860b72c8b6
pipistrello: rename sdram->ddram
2015-03-19 18:48:22 +01:00
7fa1cd72a8
fhdl/verilog: fix dummy signal initial event
2015-03-19 00:24:30 +01:00
3aee58f484
mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)
2015-03-18 18:54:22 +01:00
5a9afee234
fhdl/specials/memory: use $readmemh to initialize memories
2015-03-18 15:27:01 +01:00
c0fb0ef600
fhdl/verilog: change the way we initialize reg: reg name = init_value;
...
This allows simplifications (init in _printsync and _printinit no longer needed)
2015-03-18 15:05:26 +01:00
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
...
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
2fc2f8a6c0
migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)
2015-03-18 14:41:43 +01:00
bdc47b205a
Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"
...
This breaks simulations, and we will try to use the "reg name = value" syntax instead.
This reverts commit e946f6e453
2015-03-18 12:08:25 +01:00
89fefef3f8
genlib/io: add optional external rst to CRG
2015-03-17 16:22:22 +01:00
500e58ce7d
mibuild/platform/versa: fix clock_constraints
2015-03-17 15:25:10 +01:00
e07b7f632c
mibuild/lattice: use ODDRXD1 and new synthesis directive
2015-03-17 14:59:36 +01:00
b7d7fe1a4c
fhdl/special: add optional synthesis directive (needed by Synplify Pro)
2015-03-17 14:59:05 +01:00
022ac26c22
mibuild/lattice: add LatticeAsyncResetSynchronizer
2015-03-17 12:42:36 +01:00
c06ab82f13
mibuild/platforms/versa: add ethernet clock constraints
2015-03-17 12:04:00 +01:00
ba2aeb08be
mibuild/platforms/versa: add rst_n
2015-03-17 11:51:34 +01:00
6dd8d89c6c
mibuild/lattice: fix LatticeDDROutput
2015-03-17 09:40:25 +01:00
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
...
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
e946f6e453
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
2015-03-16 23:47:07 +01:00
b5a9909b08
mibuild/xilinx/common: add LatticeDDROutput
2015-03-16 22:57:18 +01:00
993059a59c
mibuild/xilinx/common: add XilinxDDROutput
2015-03-16 22:53:05 +01:00
69ce6dd48c
migen/genlib/io: add DDRInput and DDROutput
2015-03-16 22:47:13 +01:00
b3b1209c62
mibuild/platforms: add ethernet to versa
2015-03-16 22:24:10 +01:00
fab0b0b161
mibuild/platforms: add user_dip_btn to versa
2015-03-16 22:11:15 +01:00
d6041879dd
mibuild/lattice: use new Toolchain/Platform architecture
2015-03-16 21:24:21 +01:00
e903b62af1
mibuild/altera: use new Toolchain/Platform architecture
2015-03-16 21:07:55 +01:00
f7bfa13144
mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton)
2015-03-16 19:02:34 +01:00
beeaefccea
move pytholite to separate repos
2015-03-14 22:48:03 +01:00
c824379878
fhdl/visit: fix TransformModule
2015-03-14 17:45:11 +01:00
aef9275c99
mibuild/xilinx: export special_overrides dictionary
2015-03-14 10:45:11 +01:00
d34b7d7a6b
mibuild/xilinx: remove obsolete CRG_DS
2015-03-14 00:27:24 +01:00
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
702d177c85
mibuild: get rid of Platform factory function, cleanup
2015-03-13 23:25:15 +01:00
ff266bc2ee
migen/genlib/io: add DifferentialOutput and Xilinx implementation
2015-03-12 19:30:57 +01:00
bf28664cb4
genlib/io.py: fix copy/paste error (thanks rjo)
2015-03-12 18:49:49 +01:00
c8ba8cde8e
migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild
2015-03-12 18:38:53 +01:00
00e8616de2
mibuild/sim: clean up (thanks sb)
2015-03-10 16:41:52 +01:00
555c444da2
mibuild/sim/dut_tb: fix permissions
2015-03-10 11:06:55 +01:00
9d8f1cd61d
mibuild/sim: get serial dev from /tmp/simserial
2015-03-10 00:42:54 +01:00
70a3e8081c
mibuild/sim: add support for pty
2015-03-09 23:31:11 +01:00
aa609bee15
mibuild/sim: remove hack, the issue was in gateware (padding)
2015-03-09 20:57:20 +01:00
8e09a86e4f
genlib/misc: add increment parameter to Counter
2015-03-09 20:20:25 +01:00
ebcea3c000
fhdl/module: use r.append() in _collect_submodules
2015-03-09 19:45:02 +01:00
ee1091f491
fhdl/module: avoid flushing self._submodules and create do_exit.
2015-03-09 17:17:21 +01:00
efc5f221d9
mibuild/sim: clean up and move eth struct to sim
2015-03-09 14:40:33 +01:00
a72c091bc2
mibuild/sim: regroup console_tb/ethernet_tb in dut_tb
2015-03-09 14:40:31 +01:00
e82b540a96
mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up
2015-03-09 13:30:21 +01:00
3e84c66ba9
vivado: permit resources without pins
...
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
2015-03-09 13:30:19 +01:00
e60a97534b
mibuild/sim: able to visualize arp requests with wireshark
...
now need to find why that is not responding...
2015-03-06 20:16:30 +01:00
a64acdfa65
mibuild/sim: able to send ethernet frame from sim to server.py
2015-03-06 12:49:56 +01:00
0029b87628
mibuild/sim: add ethernet pins to verilor.py
2015-03-06 12:20:17 +01:00
Robert Jordens
Sebastien Bourdeauducq
Florent Kermarrec