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Author SHA1 Message Date
Sebastien Bourdeauducq
b469571afe move xilinx_strace_tailor to tools 2015-03-30 19:42:11 +08:00
Sebastien Bourdeauducq
c169f0b189 Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions" 
This reverts commit f03aa76292.
 2015-03-30 19:41:16 +08:00
Sebastien Bourdeauducq
dc88295338 Revert "migen/fhdl: pass fdict filename --> contents to specials" 
This reverts commit ea04947519.
 2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq
b1c811a3d1 Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method" 
This reverts commit 95cfc444e6.
 2015-03-30 19:41:04 +08:00
Florent Kermarrec
15e24b6c10 mibuild/platforms: fix minispartan6 2015-03-30 11:42:14 +02:00
Florent Kermarrec
95cfc444e6 migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method 2015-03-30 11:37:59 +02:00
Florent Kermarrec
ea04947519 migen/fhdl: pass fdict filename --> contents to specials 2015-03-30 11:37:57 +02:00
Florent Kermarrec
f03aa76292 migen: create VerilogConvert and EDIFConvert classes and return it with convert functions 2015-03-30 11:37:55 +02:00
Sebastien Bourdeauducq
21c5fb6f6c Merge branch 'master' of github.com:m-labs/migen 2015-03-30 00:52:15 +08:00
Sebastien Bourdeauducq
19a6157478 platforms/lx9_microboard,usrp_b100: fix bitgen opts 2015-03-30 00:44:56 +08:00
Florent Kermarrec
263fc47728 platforms/kc705: fix .bin generation with ISE and Vivado 2015-03-29 21:15:20 +08:00
Florent Kermarrec
b313772a0c sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00
Florent Kermarrec
17f3590a7c platforms/kc705: add iMPACT programmer 2015-03-29 12:15:39 +02:00
Florent Kermarrec
be20fbabe4 soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!) 2015-03-28 23:35:44 +01:00
Florent Kermarrec
0649ded5fd soc: simplify main_ram_size computation and share it between LASMIcon and Minicon 2015-03-28 23:10:33 +01:00
Florent Kermarrec
a8d91c0c1d sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue) 2015-03-28 16:35:15 +01:00
Florent Kermarrec
75ee8a5db9 sdram/phy/simphy: OK with DDR3 2015-03-28 01:59:55 +01:00
Florent Kermarrec
51ce7cad6f sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2 2015-03-28 01:18:35 +01:00
Florent Kermarrec
a95b3f8f13 sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it) 2015-03-28 01:17:50 +01:00
Florent Kermarrec
7fe748e1b0 sdram/module: clean up tREFI. (use 64ms/8k or 4k) 2015-03-28 01:09:21 +01:00
Sebastien Bourdeauducq
54a88da5b8 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-27 19:22:29 +01:00
Sebastien Bourdeauducq
72fae61525 Merge branch 'master' of https://github.com/m-labs/migen 2015-03-27 19:22:03 +01:00
Robert Jordens
20b646bd1a add tool to build minimal xilinx toolchains 2015-03-27 19:21:47 +01:00
Robert Jordens
54c14c7119 pipistrello: add por reset counter 
* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
 2015-03-27 19:18:11 +01:00
Florent Kermarrec
f4c35e358e software/bios/sdram: small clean up 2015-03-27 18:24:19 +01:00
Florent Kermarrec
6245dd7b6f software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6 
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
 2015-03-27 16:43:22 +01:00
Florent Kermarrec
f85a4f004b software/bios/sdram: add random addressing to memtest 
testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
 2015-03-27 15:49:16 +01:00
Florent Kermarrec
ec080479da mibuild/sim: use the same architecture we use for others backends 2015-03-27 14:14:49 +01:00
Florent Kermarrec
340014dbac targets: revert use of integers in clocks/timings 2015-03-26 23:45:35 +01:00
Florent Kermarrec
9137b91e9e sdram: remove nbits from modules and databits from GeomSettings 2015-03-26 23:27:37 +01:00
Florent Kermarrec
38d24b637e software/bios/sdram: make seed_to_data static 2015-03-26 23:05:20 +01:00
Florent Kermarrec
9a9af17aca sdram/phy/simphy: remove use of iter 2015-03-26 23:02:23 +01:00
Florent Kermarrec
e6de4b1bf9 sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16) 2015-03-26 22:28:32 +01:00
Florent Kermarrec
e79a716425 software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter) 2015-03-26 22:16:31 +01:00
Florent Kermarrec
257706517e software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation 2015-03-26 00:01:42 +01:00
Florent Kermarrec
1fc24e66dc sofware/memtest: use MAIN_RAM_SIZE from mem.h 2015-03-25 19:00:07 +01:00
Florent Kermarrec
1a1c9b4420 tools/flterm.py: small clean up 2015-03-25 18:44:08 +01:00
Florent Kermarrec
94b62eff8b libcompiler-rt: add ucmpdi2.o 2015-03-25 17:57:42 +01:00
Florent Kermarrec
69e9032d49 sofware/memtest: update bandwidth registers 2015-03-25 17:25:39 +01:00
Florent Kermarrec
ff11cb97a9 sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
Florent Kermarrec
ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec
7ea9e2ba89 sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
Florent Kermarrec
73c2b7ebaa tools: add minimal flterm.py (basic flterm.c clone with kernel loading for now) 
flterm.c is not portable, we need a portable alternative. Once flterm.py will support all flterm features, it will be possible to remove flterm.c.
 2015-03-25 16:47:03 +01:00
Florent Kermarrec
6492ef1efa linker-sdram.ld: sdram mem region is now called main_ram 2015-03-25 16:45:19 +01:00
Florent Kermarrec
de31103cce platforms/minispartan6: add ftdi_fifo pins 2015-03-22 11:20:22 +01:00
Florent Kermarrec
20207c9c32 liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6) 2015-03-22 11:11:37 +01:00
Florent Kermarrec
c77562f44b liteusb: make oe_n optional on ft2232h phy 2015-03-22 10:56:56 +01:00
Florent Kermarrec
ed5746a1fe liteusb: fix imports 2015-03-22 10:56:29 +01:00
Florent Kermarrec
200979fb81 platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz 2015-03-22 03:37:27 +01:00
Florent Kermarrec
a0ee0d8ff6 targets: add minispartan6 (SDRAM working) 2015-03-22 03:29:11 +01:00