Sebastien Bourdeauducq
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587f50cf90
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doc: new 'specials' API
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2013-02-22 18:12:42 +01:00 |
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Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
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Sebastien Bourdeauducq
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e82ea19cdc
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doc: tristates
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2013-02-19 17:52:57 +01:00 |
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Sebastien Bourdeauducq
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1b18194b1d
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fhdl: TSTriple
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2013-02-19 17:26:02 +01:00 |
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Sebastien Bourdeauducq
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dc93a231c6
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fhdl: tristate support
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2013-02-15 00:17:24 +01:00 |
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Sebastien Bourdeauducq
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63d399b6ad
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fhdl/autofragment: from_attributes
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2013-02-11 18:34:01 +01:00 |
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Sebastien Bourdeauducq
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7ff61d8930
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doc: fix signal desc layout
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2013-02-10 19:39:18 +01:00 |
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Sebastien Bourdeauducq
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d78fc48805
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Merge branch 'master' of github.com:milkymist/migen
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2013-02-10 19:03:32 +01:00 |
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Sebastien Bourdeauducq
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1794b45ed3
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doc/dataflow: remove ActorNode
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2013-02-10 19:03:18 +01:00 |
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Sebastien Bourdeauducq
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f2665efbfe
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doc/dataflow: remove ALA
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2013-02-10 18:57:03 +01:00 |
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Sebastien Bourdeauducq
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b988003878
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doc: multiple clock domains
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2013-02-10 18:56:45 +01:00 |
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Sebastien Bourdeauducq
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6bca9c8b98
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doc: do not inline examples as this never works with most Sphinx setups ...
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2013-02-10 18:45:06 +01:00 |
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Sebastien Bourdeauducq
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3f063db281
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doc: update to new Migen APIs
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2013-02-10 18:42:47 +01:00 |
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Sebastien Bourdeauducq
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92b67df41c
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sim: default runner to Icarus Verilog
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2013-02-09 17:04:53 +01:00 |
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Sebastien Bourdeauducq
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bd6856ba7a
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flow/perftools: finish removing ActorNode
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2013-02-09 17:03:48 +01:00 |
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Sebastien Bourdeauducq
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473fd20f8c
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fhdl/structure: store clock domain name
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2013-01-24 13:49:49 +01:00 |
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Sebastien Bourdeauducq
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3201554f76
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fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
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2013-01-23 15:13:06 +01:00 |
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Sebastien Bourdeauducq
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314a6c7743
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corelogic: complex arithmetic support
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2013-01-05 14:18:36 +01:00 |
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Sebastien Bourdeauducq
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badba89686
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fhdl: support nested statement lists
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2013-01-05 14:18:15 +01:00 |
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Sebastien Bourdeauducq
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47f5fc70e4
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pytholite: fix bug with constant assignment to register
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2012-12-19 16:21:57 +01:00 |
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Sebastien Bourdeauducq
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9c65402fda
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pytholite: prune unused registers
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2012-12-19 16:03:05 +01:00 |
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Sebastien Bourdeauducq
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3fae6c8f03
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Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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4d0db2cb05
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examples/pytholite: fix imports
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2012-12-16 20:26:23 +01:00 |
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Sebastien Bourdeauducq
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b06fbdedd6
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fhdl/tools: bitreverse
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2012-12-14 23:56:16 +01:00 |
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Sebastien Bourdeauducq
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1f350adf14
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actorlib/sim/SimActor: do not drive busy low when generator yields None
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2012-12-14 23:56:03 +01:00 |
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Sebastien Bourdeauducq
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a67f483f0f
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Token: support idle_wait
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2012-12-14 19:16:22 +01:00 |
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Sebastien Bourdeauducq
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6f99241585
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Move Token to migen.flow.transactions
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2012-12-14 15:55:38 +01:00 |
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Sebastien Bourdeauducq
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28b4d99d31
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replace some forgotten is_abstract()
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2012-12-12 22:36:45 +01:00 |
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Sebastien Bourdeauducq
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a7227d7d2b
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Remove ActorNode
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2012-12-12 22:20:48 +01:00 |
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Sebastien Bourdeauducq
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8163ed4828
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Merge branch 'master' of github.com:milkymist/migen
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2012-12-06 20:57:30 +01:00 |
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Sebastien Bourdeauducq
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483b821342
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fhdl/structure: do not create Signal in Instance when parameter is int
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2012-12-06 20:56:46 +01:00 |
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Sebastien Bourdeauducq
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280a87ea69
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elsewhere: do not create interface in default param
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2012-12-06 17:34:48 +01:00 |
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Sebastien Bourdeauducq
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62187aa23d
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migen/bank: do not create interface in default param
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2012-12-06 17:28:28 +01:00 |
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Sebastien Bourdeauducq
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c3fdf42825
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bus/csr: add SRAM
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2012-12-06 17:16:17 +01:00 |
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Sebastien Bourdeauducq
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e89c66bf14
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bank/csrgen: interface -> bus
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2012-12-06 17:15:34 +01:00 |
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Sebastien Bourdeauducq
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273d9d285b
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bank/description: define reset value of read signal
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2012-12-05 16:40:44 +01:00 |
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Sebastien Bourdeauducq
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34ce934809
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actorlib/sim: drive busy high until generator is finished
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2012-12-05 16:40:12 +01:00 |
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Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
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Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
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Sebastien Bourdeauducq
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adb1565d7a
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pytholite: fix bit width of selection signal
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2012-11-30 17:07:32 +01:00 |
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Sebastien Bourdeauducq
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cfb23c442f
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pytholite: support signed registers
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2012-11-30 17:07:12 +01:00 |
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Sebastien Bourdeauducq
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7093939309
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corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |
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Sebastien Bourdeauducq
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31c722f993
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corelogic/roundrobin: fix request width
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2012-11-29 23:47:08 +01:00 |
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Sebastien Bourdeauducq
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70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
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d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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070652cc39
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pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |