02d804feab
sim: accept iterables as generator list
2015-10-19 19:18:17 +08:00
0999a17319
verilog, sim: accept iterables in FHDL statements
2015-10-19 19:17:26 +08:00
4d9b2fff63
genlib/fsm: fix return value of _get_register_control
2015-10-19 19:03:43 +08:00
766b0bee65
MANIFEST.in: fix lm32 data directory
2015-10-19 16:30:41 +08:00
a824046bbc
Revert "sim/core: fix Cat bitshift"
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This reverts commit 6d6f91a02b
2015-10-19 16:08:42 +08:00
6d6f91a02b
sim/core: fix Cat bitshift
2015-10-19 16:07:45 +08:00
28962ff438
sim/core: truncate evaluated values before test in If
2015-10-19 15:58:21 +08:00
e6452166c2
software: do not build libdyld and libunwind for lm32. Closes #22
2015-10-19 11:33:21 +08:00
ec80f0fa7e
build/vivado: quote paths in Tcl (prevents problems with \ on Windows)
2015-10-19 09:40:44 +08:00
4acb7bc662
sim: support execution of nested statement lists (typo)
2015-10-15 13:53:04 +08:00
3b7f1264f1
sim: support execution of nested statement lists
2015-10-15 13:52:24 +08:00
884faedc00
integration/builder: escape backslash in makefile defines
2015-10-14 21:45:36 +08:00
48d22a7588
genlib/fifo: width_or_layout -> width
2015-10-14 21:36:44 +08:00
93a615ade4
Merge branch 'new' of github.com:m-labs/misoc into new
2015-10-14 11:11:06 +08:00
ecc4c573eb
integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
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Reported by Florent Kermarrec
2015-10-14 11:09:53 +08:00
f7787c3c13
software/bios: move romboot after serialboot and netboot
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On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 18:13:00 +02:00
9041868291
software/bios: move romboot after serialboot and netboot
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On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 17:49:29 +02:00
8817716d5f
test/divider: subtests
2015-10-13 18:39:41 +08:00
b8283ec92c
vivado progammer: allow to specify flash chip
2015-10-12 20:07:01 +02:00
e0899c1424
sim: make sure replaced memory signals are always in VCD signal set
2015-10-05 12:24:32 +08:00
e96eba4493
setup: include software and Verilog files
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Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
2015-10-05 12:08:02 +08:00
c38d8175b7
interconnect/stream: add missing part of Demultiplexer
2015-10-05 00:10:55 +02:00
af3723db14
setup: add entry points
2015-10-05 00:45:02 +08:00
5e8c4cc364
setup: fix readme
2015-10-05 00:44:50 +08:00
70e3280579
travis/conda: build for python 3.5
2015-10-05 00:25:25 +08:00
09bef1a016
travis/conda: build for python 3.5
2015-10-05 00:10:04 +08:00
b1f8aa2a67
travis: activate py35
2015-10-04 23:12:07 +08:00
d983782bed
travis: activate py35
2015-10-04 23:11:16 +08:00
6258257573
travis: python 3.5
2015-10-04 23:08:29 +08:00
4ccb489036
travis: python 3.5
2015-10-04 23:08:14 +08:00
9c905830dc
sdram: cleanup
2015-10-02 11:37:22 +08:00
d21358fc26
liteeth_mini: fix imports, replace Counter and FlipFlop
2015-09-30 20:17:52 +08:00
617c6ecb47
interconnect/stream: add multiplexer and demultiplexer
2015-09-30 19:43:51 +08:00
6c01f80fc5
genlib/fifo: add missing imports
2015-09-30 18:58:46 +08:00
0c1e1c9769
test/fifo: do not use Record
2015-09-30 17:06:31 +08:00
b3d5d1628c
interconnect/stream: remove param, do not depend on FIFO Record support
2015-09-30 16:40:34 +08:00
1b8f313d40
lasmicon: do not depend on FIFO Record support
2015-09-30 16:40:04 +08:00
4451bb20e5
genlib/fifo: remove Record support
2015-09-30 16:39:33 +08:00
c36029fa61
command line options support, CSR CSV, all targets building
2015-09-29 18:14:54 +08:00
e1927b7cbb
flterm: cleanup
2015-09-29 18:14:19 +08:00
48b6733c33
cores/gpio: fix import
2015-09-29 18:13:59 +08:00
913558ab19
build: stop at the first failed Quartus command
2015-09-29 15:53:18 +08:00
5e45b6ced6
build: add missing import for Lattice Diamond
2015-09-29 15:44:57 +08:00
6d2d70d879
fhdl/FullMemoryWE: fix clocking
2015-09-29 13:12:27 +08:00
b4c5ffc1ba
fhdl: typecheck ClockSignal and ResetSignal arguments
2015-09-29 13:11:40 +08:00
dd7dfb0d5e
soc_core: simplify settings (assume CPU and CSR present)
2015-09-29 10:19:42 +08:00
b1a90053f5
minor fixes
2015-09-29 10:19:00 +08:00
8e860e3aba
Merge branch 'master' of github.com:m-labs/misoc
2015-09-28 20:40:37 +08:00
75d927e080
Revert "Sort constants in csr generation."
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This reverts commit d628c147ec
2015-09-28 20:40:31 +08:00
7c9a7ee757
build: cleanup
2015-09-28 20:34:35 +08:00
Sebastien Bourdeauducq
Florent Kermarrec
Yann Sionneau