Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command
Tested with digilent_arty.py
Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
This allows setting a root device other than ram0, this is useful
when using a rootfs from the SD card. Doing this makes boot time
faster and saves on memory footprint used by an in ram initrd.
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.
This will be less accurate but will still provide representative results which
is the aim of this test.
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
This not only tests for the precise PHY model, but also whether there
is a model attribute in the ethphy instance and whether that is set to
True.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
The different branches each constructed their own ethphy. We can split
this out, which increases code reuse and allows to use the GMII and
XGMII interface types with all of Ethernet, Etherbone or
Ethernet+Etherbone.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
This renames the `clk_edge_t` struct to `clk_edge_state_t`, given it
only tracks the previous clock edge state.
Furthermore introduce a new `enum clk_edge` (typedef'd to
`clk_edge_t`) which represents all possible clock edges and add a
function (`clk_edge`) to retrieve the type of current clock edge as a
`clk_edge_t`.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Michal Sieron
Florent Kermarrec
George Hilliard
Leon Schuermann
Camilo Andres Vera Ruiz
Stafford Horne
Nathaniel R. Lewis
wuhanstudio
Tim Ansell
Pawel Sagan
Piotr Binkowski
Tim Callahan