a6acfb9a37
stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.
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Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
2022-09-07 08:59:37 +02:00
ce90181046
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 13:13:45 +02:00
af43e98e78
Merge branch 'naxriscv-merge'
2022-09-06 13:07:54 +02:00
5fad94f9d6
cpu/VexRiscv_SMP add --wishbone-force-32b option
2022-09-06 11:23:36 +02:00
36297c7a1e
cores/video: Avoid serializer_attrs.
2022-09-05 09:49:15 +02:00
398811b910
Merge pull request #1413 from trabucayre/gowin_HDMI
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soc/cores/video: adding Gowin HDMI Phy
2022-09-05 09:32:29 +02:00
8159b5caad
Merge pull request #1412 from umarcor/umarcor/f4pga
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litex/build/xilinx/f4pga: update imports
2022-09-02 19:03:02 +02:00
a9c7e868e7
soc/cores/video: adding Gowin HDMI Phy
2022-09-02 19:00:33 +02:00
7f17866386
litex/build/xilinx/f4pga: update imports
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Signed-off-by: umarcor <umartinezcorral@antmicro.com>
2022-09-02 15:48:22 +02:00
153182a014
cores/dna: Fix typo.
2022-09-02 13:09:40 +02:00
4426e61899
soc/add_pcie: Expose with_synchronizer parameter.
2022-09-01 17:47:27 +02:00
b24d744f8e
cores/dna: Rewrite/simplify core and use a slower clock (sys_clk/16).
2022-09-01 14:24:01 +02:00
1c4d64f46b
CHANGES: Update.
2022-09-01 11:22:25 +02:00
c0d3775dcd
integration/builder: Simplify bios_console.
2022-08-31 12:10:15 +02:00
aec02b395d
integration/builder: Add default bios_console value.
2022-08-31 10:33:26 +02:00
35afd59956
tools/litex_server/litex_client: Add initial information exchange and improve PCIe case.
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Due to the address translation done with the LitePCIe bridge (remapping CSR to 0), RemoteClient
needs to know which bridge is used to also translate CSRs.
This commit adds an initial information exchange between server and client and avoid the PCIe workarounds.
2022-08-30 18:54:03 +02:00
ea8ba57eab
Merge pull request #1410 from trabucayre/improve_connectors
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Improve connectors
2022-08-30 15:34:55 +02:00
fc0f0be679
build/generic_platform/ConnectorManager: allows to search recursively pins through connectors dictionary
2022-08-29 20:27:41 +02:00
d3368d7fab
build/generic_platform: allows to dynamically extends connectors dictionary
2022-08-29 20:25:39 +02:00
ece86a7673
integration/software: Remane BIOS console options/flags.
2022-08-29 19:47:08 +02:00
6f5412e9d0
bios/main: Change no console message display.
2022-08-29 19:31:41 +02:00
8b8dba658c
integration/builder: Rename exposed bios-console values.
2022-08-29 19:26:29 +02:00
f842481a2d
integration/builder: Rename --lto argument to --bios-lto and create BIOS group.
2022-08-29 19:01:55 +02:00
e2a3cd57bf
Merge pull request #1409 from cklarhorst/bios_no_console
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integration/builder: Make bios console configurable + add no console option
2022-08-29 18:51:31 +02:00
9e4df3c1d2
integration/builder Add no bios console option
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This allows to deactivate the cmd_handlers and the serial parsing code to reduce the bios size.
2022-08-29 10:55:39 +02:00
b010455415
integration/builder Make bios console configurable
2022-08-29 10:40:31 +02:00
50a5e137ff
Merge pull request #1405 from jrudolph/better-meson-error-msg
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soc/integration/builder: more precise error message when meson is too old
2022-08-24 19:36:23 +02:00
64e5de9fc8
soc/integration/builder: more precise error message when meson is too old
2022-08-23 19:02:41 +02:00
01754a82c8
integration/soc: fix sata irq initialization
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The first argument to `self.irq.add()` should match the name of the
`EventManager()` object being added, i.e., "sata_irq" rather than
just plain "sata". This is necessary for interrupt signals to be
asserted as intended.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-08-19 14:37:22 -04:00
78a1dbbc8b
Merge pull request #1402 from enjoy-digital/naxriscv-merge
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cpu/NaxRiscv fix LSU deadlock
2022-08-18 17:32:16 +02:00
89522f6980
cpu/NaxRiscv fix LSU deadlock
2022-08-18 10:36:19 +02:00
33ae301d0d
Merge pull request #1395 from lschuermann/dev/missing-cpus-manifest
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Add missing soc/cores/cpu directories to MANIFEST.in
2022-08-10 09:57:53 -07:00
727cc40ab1
Add missing soc/cores/cpu directories to MANIFEST.in
2022-08-09 20:30:04 +02:00
552d7bdb5c
cpu/NaxRiscv: update
2022-08-08 10:53:06 +02:00
ec4c8741d4
cpu/NaxRiscv: update
2022-08-08 10:51:23 +02:00
c4e635ea5c
Merge pull request #1393 from trabucayre/fix_vivado_yosys_synth
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build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys
2022-08-05 17:30:14 +02:00
b792bfd8b2
tools/litex_client/run_gui: Add Identifier/Leds/Buttons peripherals support.
2022-08-05 15:25:13 +02:00
ae44b70833
build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys
2022-08-05 14:51:39 +02:00
95a4814184
tools/litex_client: Improve run_gui termination.
2022-08-05 14:12:37 +02:00
68006a2144
tools/litex_client: Add XADC (7-Series) suppport to GUI.
2022-08-05 13:49:26 +02:00
ae8deda186
interconnect/axi/AXIArbiter: valid also needs to be filtered.
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Fixes un-sollicited valids on masters.
2022-08-05 11:20:52 +02:00
a286d77e01
build/xilinx/vivado: Switch from .format to f-strings.
2022-08-05 08:59:32 +02:00
2fba07daf8
build/gowin: Use build_name instead of top for generated files.
2022-08-05 08:30:34 +02:00
3c1e8e74fc
build: Cosmetic cleanups.
2022-08-05 08:22:36 +02:00
c2b62a6b0c
Merge pull request #1392 from tpwrules/fix-vexriscsmp-quartus
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cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus
2022-08-05 08:02:29 +02:00
1f2d0e120b
Merge pull request #1391 from dlobato/fix-verilator-fst-trace
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build/sim/verilator: fixed missing placeholder
2022-08-05 08:02:08 +02:00
195cc915ed
cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus
2022-08-04 21:34:56 -05:00
41e1ccce4b
build/sim/verilator: fixed missing placeholder
2022-08-04 20:03:29 +01:00
926fb9a30a
build/xilinx/vivado: Fix build.
2022-08-04 17:59:12 +02:00
47df2f6983
bios/cmd_bios: Add buttons command to get buttons value.
2022-08-04 16:31:12 +02:00
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
umarcor
Christian Klarhorst
Johannes Rudolph
Gabriel Somlo
Tim 'mithro' Ansell
Leon Schuermann
Thomas Watson
David Lobato