Florent Kermarrec
0ba9ab92b4
altera/common: fix AsyncResetSynchronizer polarity and simplify
2019-08-08 16:19:22 +02:00
Florent Kermarrec
124dff8f3f
build/xilinx/common: improve presentation
2019-08-08 16:08:55 +02:00
Florent Kermarrec
60873a5b73
microsemi/common: improve presentation
2019-08-08 16:06:40 +02:00
Florent Kermarrec
36d9d78c5e
build/altera/common: improve presentation
2019-08-08 16:02:34 +02:00
Florent Kermarrec
95953d2928
platforms/default_clk_period: use 1e9/freq
2019-08-07 08:36:04 +02:00
Florent Kermarrec
f1d8c70bd8
targets/minispartan6/crg: only keep S6PLL code
2019-08-07 08:29:59 +02:00
Florent Kermarrec
d3d0a6231c
cores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 08:29:20 +02:00
Florent Kermarrec
a881817fb3
cores/clock/s6pll: add phase support
2019-08-07 08:18:54 +02:00
Florent Kermarrec
6b7ca0cff7
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
2019-08-07 08:17:44 +02:00
Florent Kermarrec
1884649de1
litex_term: make sure to unconfigure console when board is unplugged
2019-08-06 08:46:25 +02:00
Florent Kermarrec
e052d7f645
soc/integration/builder: -x
2019-08-06 07:56:45 +02:00
Florent Kermarrec
236070fdcf
cores: -x on spi.py
2019-08-05 10:36:43 +02:00
Florent Kermarrec
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
...
Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
Florent Kermarrec
ce5c58592b
soc/cores/uart: add FT245 FIFO mode support (sync & async)
2019-08-04 12:22:35 +02:00
Florent Kermarrec
a496760cb6
build/altera/quartus: use .bat on win32/cygwin
2019-08-02 10:27:38 +02:00
Florent Kermarrec
7e0ea07076
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning
2019-08-01 21:03:05 +02:00
Florent Kermarrec
92d93ad221
cores/pwm: remove default CSR reset values.
2019-07-29 08:38:28 +02:00
Florent Kermarrec
25ca0a8b71
soc: generate git header and show migen/litex git sha1 in bios
2019-07-27 20:27:53 +02:00
enjoy-digital
ae00482dde
Merge pull request #223 from sergachev/master
...
support vivado incremental implementation
2019-07-25 20:24:25 +02:00
Ilia Sergachev
fdb119cb7b
support vivado incremental implementation
2019-07-25 19:18:11 +02:00
enjoy-digital
e637aa657b
Merge pull request #222 from antmicro/bump_vexriscv
...
cpu/vexriscv: bump submodule
2019-07-25 09:25:26 +02:00
Mateusz Holenko
932475a29b
cpu/vexriscv: bump submodule
2019-07-25 08:43:35 +02:00
Florent Kermarrec
bc7ab637dd
bios/sdram: fix compilation warning
2019-07-25 07:46:14 +02:00
Florent Kermarrec
a7895e4982
test/test_axi: remove use of rand_wait, rename rand_level to random
2019-07-23 21:02:09 +02:00
Florent Kermarrec
1cfb36e1e4
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)
2019-07-23 20:35:28 +02:00
enjoy-digital
556d2c7c0f
Merge pull request #221 from antmicro/bump_vexriscv
...
cpu/vexriscv: bump submodule
2019-07-23 12:01:13 +02:00
Mateusz Holenko
3e89c56468
cpu/vexriscv: bump submodule
2019-07-23 11:49:18 +02:00
Florent Kermarrec
e673fce445
bios/boot: fix default EMULATOR_RAM_BASE
2019-07-23 10:28:19 +02:00
Florent Kermarrec
0acacbaa82
cores/clock: cleanup
2019-07-23 09:54:30 +02:00
Florent Kermarrec
edf8aa8cfd
cores/clock: add initial iCE40 support
2019-07-23 09:27:20 +02:00
Florent Kermarrec
6d54335839
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
2019-07-22 21:55:07 +02:00
Florent Kermarrec
462d12bacc
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
2019-07-22 21:54:24 +02:00
Florent Kermarrec
fc12961e7e
soc_core: fix cpu_variant definition
2019-07-22 12:46:39 +02:00
Florent Kermarrec
af61688d1d
bios/boot: fix booting rework
...
- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
2019-07-22 11:47:41 +02:00
Florent Kermarrec
4b686dbdb2
soc_core: fix cpu_variant config (we don't want the extension)
2019-07-22 11:44:32 +02:00
enjoy-digital
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
...
Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
Florent Kermarrec
95cfd0b9e5
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)
2019-07-22 10:28:03 +02:00
Florent Kermarrec
bfdcf4b2a0
platforms/versa_ecp5: add spiflash pads
2019-07-22 10:25:55 +02:00
Florent Kermarrec
41eb21b343
soc_core: optimize mem_decoder
...
Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220 ), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.
The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
2019-07-22 08:53:54 +02:00
Florent Kermarrec
0eff65bb31
cores/up5ksram: optimize bus.adr decoding
2019-07-22 07:55:47 +02:00
Florent Kermarrec
bb99c4685a
cores/up5kspram: simplify and add support for all width/depth configurations
2019-07-21 19:28:31 +02:00
Florent Kermarrec
eaf84b8581
cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional
2019-07-20 12:57:32 +02:00
Florent Kermarrec
ea619e3afe
cores/spi: rename add_control paramter to add_csr
2019-07-20 12:56:37 +02:00
Florent Kermarrec
ec411a6ac1
soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs
2019-07-20 12:52:44 +02:00
enjoy-digital
bca42f742c
Merge pull request #219 from flammit/fix-ecp5-pll
...
soc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-07-16 07:48:22 +02:00
Mateusz Holenko
8335f13fb1
bios/boot: rework netboot/flashboot for VexRiscv in linux variant
...
Get rid of NETBOOT_LINUX_VEXRISCV/FLASHBOOT_LINUX_VEXRISCV defines
and use information about CPU_TYPE and CPU_VARIANT instead.
Use common kernel/rootfs/device tree/emulator images layout
when booting over network and from flash.
2019-07-15 16:02:58 +02:00
Mateusz Holenko
a19bdd0e6a
soc_core: generate extra string-based config defines
...
C preprocessor does not allow to compare strings, so
the current defines are not usable at the compile time.
This adds new defines that can be ifdefed.
2019-07-15 15:58:54 +02:00
Mateusz Holenko
005c07769b
soc_core: include information about cpu variant in csv and headers
2019-07-15 15:58:54 +02:00
Francis Lam
c6c743915a
soc: cores: fix name of EHXPLLL output clock in ECP5PLL
2019-07-14 12:27:28 -07:00
Florent Kermarrec
d3aaaf5e6c
cores/spi: fix/simplify loopback
2019-07-13 13:10:27 +02:00