Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
|
Sebastien Bourdeauducq
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adb1565d7a
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pytholite: fix bit width of selection signal
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2012-11-30 17:07:32 +01:00 |
|
Sebastien Bourdeauducq
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cfb23c442f
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pytholite: support signed registers
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2012-11-30 17:07:12 +01:00 |
Michael Walle
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7a1e4cb66b
|
lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.
Signed-off-by: Michael Walle <michael@walle.cc>
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2012-11-30 15:22:40 +01:00 |
|
Sebastien Bourdeauducq
|
7093939309
|
corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |
|
Sebastien Bourdeauducq
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31c722f993
|
corelogic/roundrobin: fix request width
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2012-11-29 23:47:08 +01:00 |
|
Sebastien Bourdeauducq
|
293a62dabe
|
Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 23:41:51 +01:00 |
|
Sebastien Bourdeauducq
|
8bf6945dfd
|
Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
|
Sebastien Bourdeauducq
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261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
|
Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
d8e478efee
|
Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
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070652cc39
|
pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |
|
Sebastien Bourdeauducq
|
7e2bc00c0a
|
Remove Constant
|
2012-11-28 23:18:53 +01:00 |
|
Sebastien Bourdeauducq
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fee22a4631
|
Remove Constant
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2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
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79e5f24a65
|
Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
|
2012-11-28 22:49:22 +01:00 |
|
Sebastien Bourdeauducq
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2a3ef28041
|
examples/sim/dataflow: update to new APIs
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2012-11-28 22:44:14 +01:00 |
|
Sebastien Bourdeauducq
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39d577d65e
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examples/dataflow/dma: update to new APIs
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2012-11-28 22:42:01 +01:00 |
|
Sebastien Bourdeauducq
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7c4b5931bc
|
examples/basic: remove unroll example
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2012-11-28 22:16:02 +01:00 |
|
Sebastien Bourdeauducq
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59831e0485
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fhdl/structure: improved bits_for function
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2012-11-28 18:39:44 +01:00 |
|
Sebastien Bourdeauducq
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11b1e53224
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visit/NodeTransformer: copy most nodes
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2012-11-28 17:50:55 +01:00 |
|
Sebastien Bourdeauducq
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a2bcbfdf8f
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fhdl/tools: use NodeTransformer to lower arrays
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2012-11-28 17:46:15 +01:00 |
|
Sebastien Bourdeauducq
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5440fa715c
|
examples/basic/arrays: add array assignment to fragment
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2012-11-26 22:47:35 +01:00 |
|
Sebastien Bourdeauducq
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3bc15024ac
|
fhdl/tools: use NodeVisitor
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2012-11-26 21:40:23 +01:00 |
|
Sebastien Bourdeauducq
|
e3a983d731
|
Remove unroll
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2012-11-26 20:07:48 +01:00 |
|
Sebastien Bourdeauducq
|
1460f069f6
|
fhdl/structure: remove deprecated MemoryPort
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2012-11-26 19:36:43 +01:00 |
|
Sebastien Bourdeauducq
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0620e75cb8
|
sram: do not use MemoryPort
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2012-11-26 19:32:56 +01:00 |
|
Sebastien Bourdeauducq
|
5183774ec8
|
bus/wishbone2asmi: do not use MemoryPort
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2012-11-26 19:14:59 +01:00 |
|
Sebastien Bourdeauducq
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fc85ca53ad
|
actorlib/spi: do not use MemoryPort
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2012-11-26 18:27:59 +01:00 |
|
Sebastien Bourdeauducq
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0c29775a8f
|
tb/asmicon/asmicon_wb: more complete testing by default
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2012-11-26 18:19:41 +01:00 |
|
Sebastien Bourdeauducq
|
2418367c7a
|
examples/sim/memory: do not use MemoryPort
|
2012-11-26 18:19:10 +01:00 |
|
Sebastien Bourdeauducq
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dac0d11e52
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actorlib/sim: Dumper
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2012-11-24 00:00:07 +01:00 |
|
Sebastien Bourdeauducq
|
27d87c9412
|
fhdl/structure: disable we_granularity when larger than width
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2012-11-23 23:08:12 +01:00 |
|
Sebastien Bourdeauducq
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d2c61e6a90
|
sim/generic/multiread: do not return spurious items
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2012-11-23 23:07:25 +01:00 |
|
Sebastien Bourdeauducq
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74721b206f
|
pytholite: fix import of _Slice
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2012-11-23 21:20:18 +01:00 |
|
Sebastien Bourdeauducq
|
95122bb778
|
pytholite/io: support memory
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2012-11-23 20:36:09 +01:00 |
|
Sebastien Bourdeauducq
|
f42683b71e
|
fhdl/structure/Memory: fix we width
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2012-11-23 19:21:52 +01:00 |
|
Sebastien Bourdeauducq
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784a399431
|
examples/memory: use new get_port API
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2012-11-23 19:18:08 +01:00 |
|
Sebastien Bourdeauducq
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0f6215a13a
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fhdl/structure: add Memory.get_port API
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2012-11-23 19:17:49 +01:00 |
|
Sebastien Bourdeauducq
|
9d3e218863
|
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
|
2012-11-23 18:38:03 +01:00 |
|
Sebastien Bourdeauducq
|
3971600917
|
fhdl/structure: use sets for memories and instance collections
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2012-11-23 17:20:08 +01:00 |
|
Sebastien Bourdeauducq
|
7c6ebcf753
|
examples/pytholite/uio: demonstrate memories
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2012-11-23 16:24:20 +01:00 |
|
Sebastien Bourdeauducq
|
f3efd74dfd
|
uio: support memories
|
2012-11-23 16:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
ab31b4d99c
|
bus: memory initiator
|
2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
|
0b7dd7bdce
|
pytholite/io: fix Wishbone writes + support sel attribute
|
2012-11-23 13:40:46 +01:00 |
|
Sebastien Bourdeauducq
|
20d87682ad
|
examples/pytholite/uio: simulate and convert Pytholite
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2012-11-23 13:10:40 +01:00 |
|
Sebastien Bourdeauducq
|
4c216d8f11
|
pytholite/io: support Wishbone reads
|
2012-11-23 13:09:55 +01:00 |
|
Sebastien Bourdeauducq
|
0b24a2ff36
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pytholite/io: support Wishbone writes
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2012-11-23 12:41:50 +01:00 |