Commit Graph

28 Commits

Author SHA1 Message Date
atommann 1d957d7a31
Update .gitmodules
http to https
2019-08-12 22:20:34 +08:00
Florent Kermarrec ccbf141850 compiler-rt: update to new location, fixes #209 2019-07-08 23:03:23 +02:00
Florent Kermarrec 7e837bf1d0 .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog 2019-05-24 10:39:48 +02:00
Gabriel L. Somlo 019fd94005 fixup: generated-verilog submodule for experimental Rocket support
FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
2019-05-23 18:22:37 -04:00
Florent Kermarrec d828c3a596 cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
Florent Kermarrec 3a2e283613 .gitmodules: use our VexRiscv-verilog 2019-04-27 00:00:55 +02:00
Florent Kermarrec a7378a721c .gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists. 2018-12-23 19:47:48 +01:00
Florent Kermarrec f60da4a5dc add VexRiscv submodule 2018-05-09 14:39:31 +02:00
Florent Kermarrec 1d8298af94 litex/build/sim: add tapcfg submodule for ethernet 2017-06-28 16:18:15 +02:00
Florent Kermarrec 17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec f72e172ac3 soc/software: remove libunwind 2015-11-10 12:16:34 +01:00
Florent Kermarrec 6a0f85dc42 litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
Florent Kermarrec b028569784 import misoc in litex/soc 2015-11-07 12:19:30 +01:00
Sebastien Bourdeauducq da171d8d0a Merge 'new' branch 2015-11-04 16:41:34 +08:00
Sebastien Bourdeauducq 523377efbe basic out-of-tree build support (OK on PPro) 2015-09-28 20:33:37 +08:00
Sebastien Bourdeauducq e92d00f767 move software into misoc 2015-09-28 15:30:19 +08:00
Sebastien Bourdeauducq 0f410e45f1 cores directory 2015-09-24 09:05:10 +08:00
Sebastien Bourdeauducq 83509163df reorganization WIP: flatten core structure (SDRAM still needs to be done) 2015-09-24 00:18:27 +08:00
Florent Kermarrec 3f5d475b7b remove litepcie_phy_wrappers submodule 2015-09-07 13:20:16 +02:00
whitequark f6639c1833 Add libunwind. 2015-07-26 12:59:18 +03:00
Florent Kermarrec 8a822b9deb litepcie: add litepcie_phy_wrappers to extcores 2015-04-17 13:52:21 +02:00
Sebastien Bourdeauducq 0267868cbe remove litex submodule 2015-02-25 10:40:44 -07:00
Florent Kermarrec 0a38b8c74a add LiteX external core and remove ethmac 2015-02-18 10:43:44 -07:00
Florent Kermarrec 5500c41915 move lm32/mor1kx submodules to extcores 2015-02-18 10:39:18 -07:00
Sebastien Bourdeauducq 09773df186 software: make compiler-rt a submodule 2014-11-06 18:00:28 -08:00
Sebastien Bourdeauducq 1c08aeb21c Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
Sebastien Bourdeauducq 9aa474c6f0 gitmodules: use https and m-labs 2013-12-12 15:56:06 +01:00
Sebastien Bourdeauducq 43343b131f lm32: use submodule 2013-02-24 15:57:19 +01:00