5b297f5601
soc/integration_export: Split C header generation by sections.
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- CSR Includes.
- CSR Registers/Fields Definition.
- CSR Registers Access Functions.
- CSR Registers Field Access Functions.
2024-05-21 10:26:08 +02:00
4502edd33e
soc/integration/export: Prepare split of C header generation in sections.
2024-05-21 10:26:04 +02:00
06bbbe78e4
vexii/naxii fix floating axi wires
2024-05-20 08:56:38 +02:00
21e0ec7f98
vexii/naxii fix floating axi wires
2024-05-20 08:55:05 +02:00
10083f4d87
Merge pull request #1958 from nrndda/patch-1
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Simple mistake fix
2024-05-18 21:33:25 +02:00
2d52c65613
Simple mistake fix
2024-05-18 19:09:13 +00:00
5eeb999694
update vexii
2024-05-18 16:59:27 +02:00
8c0f5447ed
fix nax/vexii git checkout process, thanks JoyBed
2024-05-18 10:01:29 +02:00
4b3f147fc8
CHANGES: Update.
2024-05-17 12:58:03 +02:00
d5f9d57c2b
Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart
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Zynqmp aximaster eth i2c uart
2024-05-17 12:54:06 +02:00
943c0c263d
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode
2024-05-17 11:02:41 +02:00
49488e5e01
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode
2024-05-17 11:02:31 +02:00
e95edaf9be
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii)
2024-05-17 11:02:16 +02:00
1986b79b9a
soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion
2024-05-17 11:02:02 +02:00
c5592ca8da
soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file
2024-05-17 11:01:46 +02:00
0720ffb404
Update vexii
2024-05-17 10:00:24 +02:00
882463d9db
Merge pull request #1955 from Dolu1990/nax64_irq
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cores/cpu/naxriscv: fix 64 bits IRQ support
2024-05-17 08:20:46 +02:00
122e060a5e
update vexii
2024-05-16 19:30:15 +02:00
74b300597b
cpu/naxriscv: fix 64 bits IRQ support
2024-05-16 18:59:40 +02:00
60b0273eda
Add baremetal IRQ support
2024-05-16 18:58:16 +02:00
57f74da8d8
Merge branch 'master' into vexiiriscv
2024-05-16 16:17:21 +02:00
d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs
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Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
2024-05-16 10:55:12 +02:00
fbf03ec74c
inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it.
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Also cleanup self.mem.get_port call.
2024-05-16 10:36:44 +02:00
c0d9224f09
integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled.
2024-05-16 09:19:18 +02:00
d4c1a10817
cores/cpu/naxriscv: Add baremetal IRQ support
2024-05-14 14:57:29 +02:00
e03b097e8e
software/libbase/isr.c: Simplify using __riscv_plic__ define.
2024-05-14 14:47:01 +02:00
c79e1ef95f
cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag.
2024-05-14 14:43:57 +02:00
786c929f08
cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE
2024-05-14 14:24:37 +02:00
8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework
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Simplify/Cleanup C exports and disable Fields accessors generation by default.
2024-05-14 12:54:48 +02:00
8eaa53ae9a
test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).
2024-05-14 12:53:09 +02:00
c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p
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Update CV32E40P to be based on the OpenHW Group's repo
2024-05-14 12:11:50 +02:00
9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p
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Fix CSR register definition for the CV32E41P core
2024-05-14 12:08:42 +02:00
46911d5078
soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects).
2024-05-14 11:59:13 +02:00
2574cc1ddc
integration/export: Fix read_function refactoring.
2024-05-14 11:55:34 +02:00
7b7334fc17
cpu/vexiiriscv update
2024-05-14 11:41:21 +02:00
29bb397bb6
soc/integration/export: Add parameter to enable/disable fields access function generation.
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Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.
This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
9f4bd5cec8
integration/export: Split get_csr_header in simpler functions.
2024-05-14 11:00:41 +02:00
c42cc350c6
integration/export: Split _get_rw_functions_c in simpler functions.
2024-05-14 10:47:38 +02:00
3506a5e82d
cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working).
2024-05-14 10:04:13 +02:00
49897ee018
software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU.
2024-05-14 10:02:56 +02:00
b0acf6136e
Fix CSR register definition for the CV32E41P core
2024-05-13 20:03:16 -04:00
41564cc47b
Update CV32E40P to be based on the OpenHW Group's repo
2024-05-13 19:59:42 -04:00
2613ae606a
interconnect/packet/Status: Simplify logic.
2024-05-13 17:52:24 +02:00
8b175c2575
CHANGES: Update.
2024-05-13 16:33:11 +02:00
0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
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Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
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Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
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Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
903c5fb9a1
handle the case when AWVALID and WVALID are not asserted at the same clock cycle
2024-05-07 13:33:04 +02:00
588b7a9519
Update Vexii
2024-05-06 19:48:56 +02:00
86a43c9ff7
integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False.
2024-05-06 14:59:17 +02:00
Florent Kermarrec
Dolu1990
Gwenhael Goavec-Merou
Dmitry
Nuntipat Narkthong
Alexey Morozov