b7b054d48e
gowin: add hack for copackaged PSRAM
...
Some Gowin FPGAs has copackaged "PSRAM" instead of "HyperRAM". They're
in fact also HyperRAM, but named differently and because of this needs
slightly changed hack.
Add hack for PSRAM too. In case of two PSRAM chips are used, the bus is
wider so the needed definition is already in place, so the bus width
hack is not needed.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2022-01-23 03:08:18 +08:00
bcc9c14c7e
cores/cpu: Fix automatic collection for Rocket/BlackParrot/EOS-S3.
2022-01-20 17:44:35 +01:00
a76828a40a
soc/add_uart: Fix uart_name="uartbone" case.
2022-01-20 10:23:06 +01:00
928ee285dc
Merge pull request #1171 from enjoy-digital/out-of-tree-cpus
...
Simplify CPUs collection and add out-of-tree support.
2022-01-20 09:46:43 +01:00
681f474c66
CHANGEs: Update.
2022-01-20 09:25:49 +01:00
bdc22770e9
cores/cpu: Deprecate external CPU class support (advantageously replaced by out-of-tree support which is more flexible).
2022-01-20 09:25:39 +01:00
c675acb868
cores/cpu: Add out-of-tree CPUs support (By searching CPUs in execution directory).
2022-01-20 09:18:10 +01:00
ba14212129
cores/cpu: Avoid duplication between CPU_GCC_TRIPLE_RISCV64/CPU_GCC_TRIPLE_RISCV32, CPU_GCC_TRIPLE_RISCV32 is just an extension of CPU_GCC_TRIPLE_RISCV64.
2022-01-20 08:49:58 +01:00
576b96ba83
cores/cpu: Switch to automatic CPUs collection.
...
Simplify code/maintenance and will also enable out-of-tree CPUs support.
2022-01-20 08:39:22 +01:00
02fe32bd79
tools/litex_server/sim: Deprecate bridge use in favor of crossover (was already supported).
2022-01-19 16:54:56 +01:00
f5e1f1c05b
soc/add_uart: Add list of supported UARTs, reorder and add error message when not supported/found.
2022-01-19 16:40:30 +01:00
3683c5b866
build/sim/platform: Add loose support to request.
2022-01-19 16:39:32 +01:00
11e8a3ce23
soc/add_uart: Simplify/Cleanup.
2022-01-19 16:06:55 +01:00
fda3164be4
soc/add_uart: Separate name/uart_name to allow multiple UARTs in the same design.
2022-01-19 15:48:42 +01:00
6d697f4506
soc/add_etherbone: Improve genericity to allow multiple instances of Etherbone cores.
...
ex:
self.submodules.ethphy0 = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks", 0),
pads = self.platform.request("eth", 0))
self.submodules.ethphy1 = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks", 1),
pads = self.platform.request("eth", 1))
self.add_etherbone(name="etherbone0", phy=self.ethphy0, phy_cd="ethphy0_eth")
self.add_etherbone(name="etherbone1", phy=self.ethphy1, phy_cd="ethphy1_eth")
2022-01-19 15:07:55 +01:00
2a17214813
Merge pull request #1169 from sergachev/fix/zynq_software
...
Fix Zynq software support
2022-01-19 10:04:48 +01:00
2f433611dd
litex_sim: Add .json support for --rom/ram/sdram-init.
2022-01-19 09:58:38 +01:00
77b2ae14bb
integration/common/get_mem_data: Add proper support for .json.
...
- Path is relative in boot.json files.
- Add optional offset (useful when used to initialize a RAM without mapping offset).
2022-01-19 09:38:53 +01:00
6a395fa492
cpu/zynq7000: correct address map
2022-01-19 02:48:13 +01:00
2bc1c3ac99
cpu/zynq7000: enable software compilation
2022-01-19 02:47:18 +01:00
682e4e0b7d
cpu/zynq7000: add boot helper
2022-01-19 02:46:49 +01:00
e9aa747d2b
cpu/vexriscv_smp/args_fill: Fill args in cpu group.
2022-01-18 18:56:02 +01:00
2913f2ecd9
tools/litex_sim: Use new verilator_build_args/argdict.
2022-01-18 18:47:40 +01:00
3d8ffa1897
build/sim/verilator: Add verilator_build_args/argdict to reduce duplication in sim targets.
2022-01-18 18:47:12 +01:00
8289e71ea7
tools/litex_sim: Remove ident_version (now provived by kwargs).
2022-01-18 17:18:50 +01:00
ae70023f0d
soc_core: Switch from --ident-version parameter to --no-ident-version.
...
Identifier version is enabled by default and we just need to allow user to easily disable it for determinist builds.
The custom --no-ident-version added to targets can then be avoided with this and this argument will
now be available on all targets.
2022-01-18 14:07:26 +01:00
07c7f664cf
integration/soc/add_sdram: Set default l2_cache_reverse value to False.
...
For correct operation of Framebuffer + CPU writes, l2_cache_reverse has to be
set to False on targets. Set it to False by default in LiteX to avoid this.
2022-01-18 11:34:12 +01:00
b958453105
soc/add_video_framebuffer: Use clock_faster_than_sys when equal.
2022-01-17 18:19:23 +01:00
15045e96f0
cores/video: Switch 1920x1080@60Hz pix_clk to 148.5MHz.
2022-01-17 18:19:19 +01:00
04e9af9fef
core/video/VideoS7GTPHDMIPHY: Swap R/B components.
2022-01-17 18:19:15 +01:00
3d3229fb49
Merge pull request #1166 from gsomlo/gls-fatfs-sd-sata
...
RFC: software/fatfs: allow sata, [spi]sdcard disk ops to co-exist
2022-01-17 10:59:57 +01:00
0eded56afa
CHANGES: Start listing changes since 2021.12.
2022-01-17 10:17:10 +01:00
5e86e14299
Merge pull request #1162 from sergachev/eos_s3_software
...
QuickLogic EOS S3 ARM software support
2022-01-17 09:53:30 +01:00
9f1a847e93
litex_setup: Add Marocchino CPU to full install.
2022-01-17 09:02:34 +01:00
1c82b20fcb
Merge pull request #1161 from stffrdhrn/or1k-marocchino
...
marocchino: Add initial support for new OpenRISC core
2022-01-17 08:59:30 +01:00
672d1dd741
build/xilinx/symbiflow: Align devices.
2022-01-17 08:17:04 +01:00
4a3cd561c4
Merge pull request #1165 from bl0x/digilent_cmod_a7
...
digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-17 08:12:10 +01:00
87bd29fec2
software/fatfs: allow sata, [spi]sdcard disk ops to co-exist
...
At the moment, sata and [spi]sdcard fatfs disk access methods
are mutually exclusive, as their names collide with each other.
Implement a DISKOPS structure with media-specific disk access
methods, and a way for the boot code to specifiy which media
type's methods to use when loading files into RAM at boot time.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-01-16 20:14:52 -05:00
4aff26ccaf
tools/litex_json2dts_linux.py: add mmc voltage regulator
...
Add MMC voltage regulator, and reference it from the mmc node.
For now, all boards we know of provide a 3.3V fixed voltage to
their SDCard receptacles, either directly or via PMOD.
2022-01-16 19:53:36 -05:00
1011b817c8
bios/boot: fix width of sata `length` variable
2022-01-16 19:46:19 -05:00
27ccb3e776
cpu/serv: Add intial MDU support (mdu variant).
2022-01-16 19:58:09 +01:00
b42525b462
add missing newline
2022-01-16 12:55:54 +01:00
881d457fbe
digilent_cmod_a7: Add xc7a35tcpg236-1 symbiflow_device.
2022-01-16 12:15:50 +01:00
0ba065db8a
cores/cpu/eos_s3: enable software support
2022-01-15 17:23:56 +01:00
d4a53b4d6d
software/bios: make makefile more universal and compact
2022-01-15 17:23:07 +01:00
cf8545c8ef
software/bios: enable map file generation
2022-01-15 17:22:46 +01:00
f07fb4e1e3
cores/cpu: rename eos-s3 to eos_s3 for compatibility
2022-01-15 17:16:48 +01:00
00dfaa1740
software/bios: place eos s3 interrupt table at .text start when present
2022-01-15 17:15:25 +01:00
15a927bcc8
libcompiler_rt: add more arm math ops
2022-01-15 17:14:38 +01:00
db9d40a5a0
integration/soc: warn about overrides only on differences
2022-01-15 17:13:48 +01:00
Icenowy Zheng
Florent Kermarrec
Ilia Sergachev
Gabriel Somlo
Bastian Löher