bcf62997f6
fhdl/bitcontainer: remove fiter
2015-09-17 17:22:03 +08:00
c2109f8f81
minor bugfixes
2015-09-17 15:20:27 +08:00
6e08df75ee
sim: support eval of slice, cat and mux
2015-09-17 14:39:36 +08:00
9dd3200ba2
fhdl/structure: fix namespace pollution
2015-09-17 14:39:17 +08:00
6569c516a1
test: bit reverse
2015-09-17 14:38:55 +08:00
0a92e346d3
fhdl/bitcontainer: remove fslice and freversed
2015-09-17 14:38:33 +08:00
fd88b9b8a3
test/constant: use new API
2015-09-17 11:08:40 +08:00
74c9159a01
add unittests for Constant
2015-09-17 11:06:04 +08:00
f5ab734bdf
fhdl/verilog: fix case value sort
2015-09-17 08:03:48 +08:00
e940c6d9b9
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
2015-09-15 12:38:02 +08:00
42afba2bbc
fhdl/decorators: remove traces of deprecated API
2015-09-12 19:44:35 +08:00
eb921fb957
genlib: remove reverse_bytes, FlipFlop, Counter
2015-09-12 19:40:29 +08:00
9667d61e84
genlib: cleanup CRG
2015-09-12 19:40:07 +08:00
1bdb9bee22
fhdl/decorators: remove deprecated API
2015-09-12 19:34:44 +08:00
336728413a
simplify imports, migen.fhdl.std -> migen
2015-09-12 19:34:07 +08:00
b43495aab1
build/xilinx: minor cleanup
2015-09-12 16:48:25 +08:00
047d1f48b5
test/support,signed,sort: use new simulator
2015-09-12 16:28:21 +08:00
8ee361ffe2
sim: refactor comb commit
2015-09-12 16:27:59 +08:00
5fa7f7414f
sim: support eval of nested lists
2015-09-12 16:01:53 +08:00
9556c335ea
genlib/sort: remove unneeded import
2015-09-12 15:21:42 +08:00
fa6d96bb9a
test/examples: do not attempt to run deleted examples
2015-09-12 15:13:45 +08:00
7bd72a16df
sim: support clock domains without sync
2015-09-12 15:12:57 +08:00
fd986210f8
simulator: support generators
2015-09-10 21:44:14 -07:00
10d89d81f4
new simulator: basic execution
2015-09-10 20:33:45 -07:00
49ef182305
fhdl/tools: add input lister
2015-09-10 20:33:10 -07:00
f9849fb8be
style
2015-09-10 20:32:47 -07:00
714ae43ab8
fhdl: remove features new simulator won't use
2015-09-10 18:29:57 -07:00
91ab3f0d01
remove genlib.misc.optree (use reduce instead)
2015-09-10 13:56:56 -07:00
1dcd2ac1c0
fixed bug in value_bits_sign of mul operatiors
2015-09-10 10:53:26 -07:00
86f34e82c3
mibuild -> migen.build
2015-09-10 10:53:15 -07:00
f1dc008d32
Simulator will be rewritten
2015-09-05 15:07:00 -06:00
dec2e23fc7
Remove code that will be into MiSoC or other packages.
2015-09-05 15:06:04 -06:00
5253b0c06e
migen/actorlib/packet: fix source.error in Depacketizer
2015-08-19 01:12:07 +02:00
646667213e
migen/flow/actor: fix sop/eop validation in PipelinedActor (stb can be inactive when pipe_ce is active)
2015-08-09 19:54:38 +02:00
f32f9be17a
resetless -> reset_less
2015-07-27 11:46:11 +08:00
cc6877df9e
fhdl: allow use of ResetSignal() on resetless clock domains
2015-07-27 01:51:52 +08:00
5a535ef347
Revert "migen/actorlib/fifo: add FIFO wrapper function"
...
This reverts commit d0a19c4be8
2015-07-24 19:25:36 +08:00
d0a19c4be8
migen/actorlib/fifo: add FIFO wrapper function
...
Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
2015-07-24 13:02:54 +02:00
1f1ff5a5e9
migen/fhdl/tools: fix rename_clock_domain when new == old
...
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
5713ae381a
actorlib/packet/Depacketizer: manage layouts without error signal
2015-07-22 21:43:21 +02:00
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
71627cf9f0
bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)
2015-06-19 08:37:16 +02:00
f8b1152b98
wishbone: add Cache (from WB2LASMI)
2015-06-17 15:31:49 +02:00
33b536e505
migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter)
2015-06-02 19:29:38 +02:00
79624ce849
migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)
2015-06-02 19:26:42 +02:00
fd16b66bdf
genlib/cdc: add BusSynchronizer
2015-06-02 17:40:42 +08:00
a5f495aeac
fhdl/verilog: add reserved keywords
2015-05-23 14:01:08 +02:00
9cabcf14e9
migen/genlib/record: add leave_out parameter to connect
...
Modules doing dataflow adaptation often need to connect most of the signals between endpoints except the one concerned by the adaptation.
This new parameter ease that by avoid manual connection of all signals.
2015-05-23 13:59:09 +02:00
f6624b34f0
migen/actorlib/spi: apply missing CSR renaming
2015-05-13 10:17:31 +02:00
76302d7aa6
vpi: cleanup (thanks sb)
2015-05-13 10:13:14 +02:00
Sebastien Bourdeauducq
Robert Jordens
Yves Delley
Florent Kermarrec