Florent Kermarrec
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1a92489555
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soc/tools/remote: add comm_pcie and comm_udp (to be tested)
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2015-11-17 15:07:00 +01:00 |
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Florent Kermarrec
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d6fdd76930
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soc/tools/remote: small cleanup and remove csr_data_width from server side
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2015-11-17 11:35:22 +01:00 |
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Florent Kermarrec
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71483b8935
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soc/tools: initialize wishbone remote control (for now only uart)
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2015-11-17 01:05:52 +01:00 |
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Florent Kermarrec
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1cde84dccf
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soc/cores/uart remove software (will be re-written and will move to soc/tools)
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2015-11-16 17:07:22 +01:00 |
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Florent Kermarrec
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1f80bb9561
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soc/interconnect/stream_packet: remove Counter
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2015-11-16 16:53:23 +01:00 |
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Florent Kermarrec
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ec35290c45
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soc/interconnect/wishbonebridge: remove Counter
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2015-11-16 16:48:37 +01:00 |
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Florent Kermarrec
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2f52d364af
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soc/interconnect/stream/SyncFIFO: expose fifo level
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2015-11-16 16:11:31 +01:00 |
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Florent Kermarrec
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7ed2576ce1
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soc/integration/cpu_interface: add bases, constants and memories output to csv files
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2015-11-15 00:04:44 +01:00 |
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Florent Kermarrec
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af909b43d5
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soc/cores/uart: add UARTWishboneBridgeDriver software
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2015-11-14 21:23:20 +01:00 |
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Florent Kermarrec
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3a2e6117f4
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soc/interconnect/stream: add Cast and others small fixes
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2015-11-14 12:17:09 +01:00 |
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Florent Kermarrec
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041483dbe1
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soc/integration/builder: only copy Makefiles when not using symlinks
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2015-11-14 03:36:46 +01:00 |
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Florent Kermarrec
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a2aa5726bf
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soc/cores: remove liteeth_mini and use liteeth
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2015-11-14 03:22:43 +01:00 |
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Florent Kermarrec
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16ba646b1b
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add TODOs
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2015-11-14 03:15:10 +01:00 |
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Florent Kermarrec
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cf4c7da2e7
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fix soc/integration/soc_core.py
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2015-11-14 02:44:12 +01:00 |
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Florent Kermarrec
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032f5a9620
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soc/interconnect: add stream_sim
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2015-11-14 00:43:49 +01:00 |
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Florent Kermarrec
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ba959c832d
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soc/interconnect: rename packet to stream_packet
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2015-11-14 00:42:58 +01:00 |
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Florent Kermarrec
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fc3ffe87ac
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for now use our fork of migen (to be able to simulate our designs)
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2015-11-13 18:31:46 +01:00 |
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Florent Kermarrec
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7d6cee6751
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soc/interconnect/stream: add BufferizeEndpoints
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2015-11-12 18:54:15 +01:00 |
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Florent Kermarrec
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83427c87cd
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soc/interconnect/stream: add Pipeline
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2015-11-12 01:41:23 +01:00 |
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Florent Kermarrec
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81c6facca2
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soc/interconnect/stream: reintroduce params
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2015-11-12 01:12:15 +01:00 |
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Florent Kermarrec
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f6b30fcae2
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soc/interconnect: add packet
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2015-11-12 00:54:40 +01:00 |
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Florent Kermarrec
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525da89c7d
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soc/interconnect: add wishbonebridge and uart bridge
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2015-11-12 00:52:36 +01:00 |
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Florent Kermarrec
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89b189ce4a
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soc/interconnect/stream: reintroduce PipelinedActor/Buffer
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2015-11-12 00:51:32 +01:00 |
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Florent Kermarrec
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194e6137ae
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soc/integration/soc_core: add support for SoCs without CPU
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2015-11-12 00:50:23 +01:00 |
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Florent Kermarrec
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352cb91688
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soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
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2015-11-11 17:37:28 +01:00 |
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Florent Kermarrec
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1f6983da2c
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soc/cores/liteeth_mini: add phy model for verilator simulation
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2015-11-11 14:22:27 +01:00 |
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Florent Kermarrec
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481163b233
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soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
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2015-11-11 14:01:48 +01:00 |
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Florent Kermarrec
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714a3d88e2
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add LICENSE, update copyrights, add Migen install instructions
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2015-11-11 13:22:39 +01:00 |
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Florent Kermarrec
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bda196fbc8
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soc/software/bios/sdram: split memtest and allow external #define of memtest sizes
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2015-11-11 13:10:03 +01:00 |
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Florent Kermarrec
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619cd8e695
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avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
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2015-11-11 12:10:55 +01:00 |
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Florent Kermarrec
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3f43a49382
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soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
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2015-11-10 16:51:51 +01:00 |
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Florent Kermarrec
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3297210e48
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boards/targets/sim: get SDRAM working in simulation with sdram/model
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2015-11-10 12:57:23 +01:00 |
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Florent Kermarrec
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4afe4a07e4
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soc/software: remove memtest (should be re-written)
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2015-11-10 12:22:08 +01:00 |
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Florent Kermarrec
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6764c06b62
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soc/sofware: remove libdyld
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2015-11-10 12:21:23 +01:00 |
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Florent Kermarrec
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f72e172ac3
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soc/software: remove libunwind
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2015-11-10 12:16:34 +01:00 |
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Florent Kermarrec
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a775672314
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litex: get verilator simulation working and add sim target as example
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2015-11-07 23:51:37 +01:00 |
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Florent Kermarrec
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6a0f85dc42
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litex: reorganize things, first work working version
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2015-11-07 17:48:55 +01:00 |
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Florent Kermarrec
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b028569784
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import misoc in litex/soc
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2015-11-07 12:19:30 +01:00 |
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