Sebastien Bourdeauducq
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c08687b9c6
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bus/dfi: filter signals by direction
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2012-02-15 21:48:05 +01:00 |
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Sebastien Bourdeauducq
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ef7aea0f31
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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
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2012-02-15 18:23:31 +01:00 |
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Sebastien Bourdeauducq
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fa9cf3e466
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bus: add DFI
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2012-02-15 18:09:14 +01:00 |
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Sebastien Bourdeauducq
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859c9d8849
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Use new bus API
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2012-02-15 16:55:13 +01:00 |
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Sebastien Bourdeauducq
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91e279ee04
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bank/csrgen: use new bus API
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2012-02-15 16:42:17 +01:00 |
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Sebastien Bourdeauducq
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af5230c8ee
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bus: fix simple interconnect
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2012-02-15 16:42:05 +01:00 |
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Sebastien Bourdeauducq
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0493212124
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bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
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Sebastien Bourdeauducq
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1368b666df
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s6ddrphy: prepare quilt
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2012-02-14 15:52:39 +01:00 |
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Sebastien Bourdeauducq
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b157d84434
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README
|
2012-02-14 15:43:09 +01:00 |
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Sebastien Bourdeauducq
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46b1f74e98
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bus/asmibus/hub: forward data and tag_call
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2012-02-14 14:00:17 +01:00 |
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Sebastien Bourdeauducq
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aef2e4b5e8
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Use double quotes for all strings
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2012-02-14 13:15:00 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
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Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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5165ff7ec3
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Include Wishbone to ASMI bridge
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2012-02-13 23:12:57 +01:00 |
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Sebastien Bourdeauducq
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e11d9b9322
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bus/wishbone2asmi: cache hits working
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2012-02-13 23:11:16 +01:00 |
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Sebastien Bourdeauducq
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1662e1b3bc
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corelogic: support reverse in displacer/chooser
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2012-02-13 23:10:27 +01:00 |
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Sebastien Bourdeauducq
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264be80f2d
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Fix syntax errors and other stupid problems
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2012-02-13 22:28:02 +01:00 |
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Sebastien Bourdeauducq
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8a61d9d121
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
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Sebastien Bourdeauducq
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d6da88d11d
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doc: update ASMI description
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2012-02-13 17:23:32 +01:00 |
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Sebastien Bourdeauducq
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060426cb59
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bus/wishbone2asmi: set WM, and send 0 when inactive
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2012-02-13 16:49:43 +01:00 |
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Sebastien Bourdeauducq
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cad9d3b960
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bus: Wishbone to ASMI caching bridge (untested)
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2012-02-13 16:29:38 +01:00 |
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Sebastien Bourdeauducq
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244bf17db7
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corelogic/misc: displacer + chooser
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2012-02-11 20:57:08 +01:00 |
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Sebastien Bourdeauducq
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e10e4360f3
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corelogic/misc/multimux: less confusing variable name
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2012-02-11 20:56:51 +01:00 |
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Sebastien Bourdeauducq
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7894411418
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bus/asmibus: fix typo
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2012-02-11 20:56:01 +01:00 |
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Sebastien Bourdeauducq
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28b0c340af
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corelogic/record: add to_signal convenience function
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2012-02-11 20:55:23 +01:00 |
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Sebastien Bourdeauducq
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e62ac1d3a1
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corelogic/misc: contiguous split
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2012-02-11 11:52:15 +01:00 |
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Sebastien Bourdeauducq
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ef436a1ec9
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bus/asmibus: add get_slots, fix get_fragment
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2012-02-10 17:49:06 +01:00 |
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Sebastien Bourdeauducq
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945d655d45
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bus: ASMI hub (untested)
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2012-02-10 15:21:04 +01:00 |
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Sebastien Bourdeauducq
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c1bff38861
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doc: update Bank description
|
2012-02-08 19:26:56 +01:00 |
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Sebastien Bourdeauducq
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0654bf4583
|
tools: use install and /usr/local (as suggested by David Kuehling)
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2012-02-08 15:09:07 +01:00 |
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Sebastien Bourdeauducq
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bfd2bf4ed3
|
tools: remove bin2hex
|
2012-02-08 15:08:03 +01:00 |
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Sebastien Bourdeauducq
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755079d7fa
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libbase: blocking UART write if IRQs are enabled
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2012-02-07 15:12:27 +01:00 |
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Sebastien Bourdeauducq
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73fce59631
|
software: shell from original BIOS
|
2012-02-07 15:02:44 +01:00 |
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Sebastien Bourdeauducq
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ef0667d959
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software: UART RX demo
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2012-02-07 14:12:33 +01:00 |
|
Sebastien Bourdeauducq
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506ffab11a
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uart: RX support
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2012-02-07 14:12:23 +01:00 |
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Sebastien Bourdeauducq
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fb22edc06a
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software: enable -Wmissing-prototypes
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2012-02-07 13:02:06 +01:00 |
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Sebastien Bourdeauducq
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63f6dece56
|
software: use the Clang/LLVM compiler
|
2012-02-07 12:52:34 +01:00 |
|
Sebastien Bourdeauducq
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a40b0ea175
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software: fix size_t and ptrdiff_t
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2012-02-07 12:06:49 +01:00 |
|
Sebastien Bourdeauducq
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494c383fa8
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software: remove unnecessary IRQ acks
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2012-02-07 00:07:25 +01:00 |
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Sebastien Bourdeauducq
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b6b1901bb8
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LM32: make IP read-only and interrupt lines level-sensitive
|
2012-02-07 00:07:12 +01:00 |
|
Sebastien Bourdeauducq
|
4aaf48afb0
|
software: interrupt driven UART working
|
2012-02-06 23:53:29 +01:00 |
|
Sebastien Bourdeauducq
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58f4f78d2c
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sram: fix sub-word write
|
2012-02-06 23:13:35 +01:00 |
|
Sebastien Bourdeauducq
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47883675db
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bus/wishbone2csr: truncate WB data
|
2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
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1eb348c573
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fhdl: do not attempt slicing non-array signals to keep Verilog happy
|
2012-02-06 18:07:02 +01:00 |
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Sebastien Bourdeauducq
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5cde57cb65
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software: use new UART
|
2012-02-06 17:53:41 +01:00 |
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Sebastien Bourdeauducq
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33f1c456bf
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top: connect UART IRQ
|
2012-02-06 17:45:40 +01:00 |
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Sebastien Bourdeauducq
|
5dc875de69
|
UART: use new bank API and event manager
|
2012-02-06 17:45:31 +01:00 |
|
Sebastien Bourdeauducq
|
fcd6583cbb
|
bank: event manager
|
2012-02-06 17:39:32 +01:00 |
|
Sebastien Bourdeauducq
|
3a2a0c4dd8
|
bank: support registers larger than the bus word width
|
2012-02-06 16:15:27 +01:00 |
|
Sebastien Bourdeauducq
|
f3ddfffc47
|
bank: refactoring
|
2012-02-06 13:55:50 +01:00 |
|
Sebastien Bourdeauducq
|
1a86f26a66
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bank/csrgen: use enumerate
|
2012-02-06 11:18:30 +01:00 |