Commit Graph

36 Commits

Author SHA1 Message Date
Florent Kermarrec c8bcbfb855 litesata: pep8 (E261, E271) 2015-04-13 15:51:17 +02:00
Florent Kermarrec 2e5501933a litesata: pep8 (W292) 2015-04-13 15:44:52 +02:00
Florent Kermarrec ea67080462 litesata: pep8 (E225) 2015-04-13 15:44:04 +02:00
Florent Kermarrec a9b42161c0 litesata: pep8 (E222) 2015-04-13 15:29:34 +02:00
Florent Kermarrec 77cdb953ad litesata: pep8 (E401) 2015-04-13 15:27:36 +02:00
Florent Kermarrec 8f7751e412 litesata: pep8 (E203) 2015-04-13 15:25:40 +02:00
Florent Kermarrec 61fa72b655 litesata: pep8 (E231) 2015-04-13 15:19:34 +02:00
Florent Kermarrec d0c5bd377a litesata: pep8 (E302) 2015-04-13 15:12:39 +02:00
Florent Kermarrec 808e1fe866 litesata: pep8 (replace tabs with spaces) 2015-04-13 14:59:00 +02:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
Florent Kermarrec 60124be293 adapt LiteSATA to new SoC 2015-04-01 22:52:19 +02:00
Sebastien Bourdeauducq 6e2a662dd7 litesata: adapt to new SoC API 2015-04-01 17:37:53 +08:00
Florent Kermarrec 9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec d8b59c03a2 litesata: avoid hack on kc705 platform with new mibuild toolchain management 2015-03-14 01:08:36 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Sebastien Bourdeauducq 073641faa1 litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec f27e7a4b22 litesata: remove unneeded clock constraint 2015-03-03 10:24:05 +01:00
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec 9e01bf5fdd litesata: create example design derived from SoC 2015-03-01 11:33:38 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec 7b464b2b1c litesata: create specialized kc705 platform to avoid duplicating things already in mibuild 2015-03-01 11:03:15 +01:00
Florent Kermarrec b34be816ec liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 8e67d6e69f liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
Florent Kermarrec 0dfca49e68 litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
Florent Kermarrec b6358be0a1 merge litesata 2015-02-28 10:48:08 +01:00