341850939e
Merge pull request #1643 from jeremyherbert/bitbang-docs
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add docstrings to bitbang
2023-03-14 09:36:38 +01:00
1256ca3767
small doc fixes, add type hints and PEP8 whitespace
2023-03-14 12:04:06 +10:00
9e08d96cb2
Merge pull request #1647 from te-johan/efinix_spi_mode
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build/efinix: add option use active or passive spi mode.
2023-03-13 21:17:02 +01:00
c2ea83db38
Merge pull request #1646 from Icenowy/gw2ar
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soc/cores/clock/gowin_gw2a: enable GW2AR support
2023-03-13 21:12:00 +01:00
60557b9e27
build/efinix: add option use active or passive spi mode.
2023-03-13 15:53:57 +01:00
b05c306908
soc/cores/clock/gowin_gw2a: enable GW2AR support
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Gowin GW2AR is just GW2A with co-packaged external RAM.
Enable using GW2APLL for GW2AR.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 16:46:31 +08:00
c64c89c652
add docstrings to bitbang
2023-03-11 13:41:10 +10:00
67e8d77421
tools/litex_sim: Update Video Framebuffer.
2023-03-10 13:33:55 +01:00
7bd98cf5d9
tools/litex_json2dts_linux: Fix intc0 regression.
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Introduced when disabling lintc0 generation on Rocket.
2023-03-10 09:34:00 +01:00
a31df7616f
cva6: Fix SRAM compile on FPGA
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-09 12:20:37 +01:00
d137416739
cva6: Adding missing common_cells sources
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-09 11:49:07 +01:00
d90f8809b4
cva6: Improving JTAG debug support
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-09 11:49:07 +01:00
6a73e4c5fb
CVA6: Adding RV32 support
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-09 11:49:07 +01:00
fb1cd22ac2
Merge pull request #1638 from gatecat/jtagremote_fix
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jtagremote: Add to Makefile and fix build
2023-03-08 18:47:52 +01:00
c2325983d5
litex_sim/video: Cleanup and directly reuse VideoGenericPHY.
2023-03-08 18:45:52 +01:00
a5d85518c9
jtagremote: Add to Makefile and fix build
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-08 13:06:16 +01:00
c8dcc39957
Merge pull request #1632 from jorislee/master
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soc/cores/cpu/vexriscv_smp/core.py: fix variants for external incoming values and remove default timer0 and uart in standard mode.
2023-03-06 09:03:55 +01:00
847fac0a81
Merge pull request #1631 from trabucayre/fix_get_extension
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add a proxy method to access bitstream extension
2023-03-06 09:03:25 +01:00
5c644aeabc
fix/VexRiscvSMP_Standard_mode_update
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Fix: VexRiscvSMP core variant defaults to incoming values and removes default timer0 and uart in standard mode.
2023-03-06 14:17:12 +08:00
c40963531c
build/generic_platform build/xxx/platform soc/integration/builder:
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generic_platform add a method to return extension for sram/flash
vendor platform: bitstream_ext -> _bitstream_ext and replace by a dict
when extension depends on mode
builder: use `get_bitstream_extension` instead of directly using
bitstream_ext
2023-03-04 11:36:29 +01:00
1ea94ca264
build/anlogic/platform: fix extension format fs -> bit
2023-03-04 11:25:46 +01:00
2d9c880cf2
Merge pull request #1629 from trabucayre/fix_efinix_ifacewriter
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build/efinix/efinity: delays iface.py execution after project xml was written
2023-03-02 09:14:08 +01:00
b28598289e
build/efinix/efinity: delays iface.py execution after project xml was written
2023-03-02 08:42:59 +01:00
ea2171d32b
tools/litex_sim: Fix --with-etherbone --with-ethernet case (thanks @g2gps).
2023-03-01 14:49:08 +01:00
b5fe30d694
build/xilinx/platform: Add XilinxUS/USPPlatform.
2023-03-01 09:36:56 +01:00
90cf730b6a
Merge pull request #1625 from AEW2015/master
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Added US pritmives for Artix+
2023-02-28 22:10:37 +01:00
7da9199ea5
Added US pritmives for Artix+
2023-02-28 13:20:26 -07:00
2f5481dbb9
gen/common: Add Unsigned/Signed Signal wrappers.
2023-02-28 10:17:16 +01:00
6ac8e9ec1f
Merge pull request #1616 from shenki/reinstate-cpu-tests
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test: Reinstate microwatt and neorv32
2023-02-28 09:19:01 +01:00
2b6fcf0b90
README/sponsors: Update.
2023-02-27 11:19:21 +01:00
4207c37288
README/sponsors: Update.
2023-02-27 11:04:23 +01:00
991198ec2e
tools/litex_json2dts_linux: Only generate lintc0 for rocket for now.
2023-02-27 09:13:45 +01:00
3922359ba1
test: Reinstate microwatt and neorv32
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They appear to be passing CI again.
Signed-off-by: Joel Stanley <joel@jms.id.au>
2023-02-27 17:46:41 +10:30
93632465a0
Merge pull request #1540 from sensille/soc_odd_regions
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soc: allow regions that are not a power of 2
2023-02-24 10:30:47 +01:00
2abb419bee
Merge branch 'master' into soc_odd_regions
2023-02-24 10:30:34 +01:00
50822c080f
cores/gpio: Move self.ev.finalize after for loop.
2023-02-24 08:37:23 +01:00
8d3c03da08
Merge pull request #1613 from adamhlt/master
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Fix GPIO IRQ CSR generation
2023-02-24 08:36:18 +01:00
ce087640ed
Fix GPIO IRQ CSR generation
2023-02-23 17:08:08 +01:00
aef23c001a
README: Add first list of sponsors/partners.
2023-02-22 19:50:52 +01:00
51326b93a5
cpu/vexriscv: Fix missing add_soc_component update.
2023-02-21 10:37:09 +01:00
45b9636902
integration/soc: Avoid soc_region_cls workaround and update CPUs.
2023-02-21 09:43:17 +01:00
c1ee154340
global: Move Open definition to gen/common and use it.
2023-02-21 09:10:15 +01:00
653b74fe98
gen/fhdl/module: Fix typo.
2023-02-21 08:26:21 +01:00
22b61c39ca
cpu/rocket: Fix arch (thanks @gsomlo).
2023-02-20 19:28:23 +01:00
2274addd8f
cpu/rocket: Check/Fix opensbi region (thanks to @gsomlo).
2023-02-20 15:44:23 +01:00
a3fbd9794c
cpu/naxriscv: Generate CPU_MMU config based on xlen.
2023-02-20 15:12:43 +01:00
0f000a0a90
cores/cpu/json2dts: Add CPU_MMU config in cores and add initial NaxRisv support to json2dts.
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Also do minor cleanups by regrouping CPU parameters at the top.
2023-02-20 14:49:35 +01:00
019fac5653
cores/cpu: Switch to soc.bus.add_region instead or add_memory_region (now prefered).
2023-02-20 11:19:12 +01:00
01e9a54321
tools/litex_json2dts_linux: Add initial CLINT DTS generation.
2023-02-20 11:04:37 +01:00
ea308ea5b1
cpu/rocket: Use correct mapping for clint/plic.
2023-02-20 10:56:37 +01:00
enjoy-digital
Jeremy Herbert
Johan Carlsson
Icenowy Zheng
gatecat
Joris Lee
Gwenhael Goavec-Merou
AEW2015
Joel Stanley
Adam Henault