Sebastien Bourdeauducq
|
d8d4e81b6e
|
bank/csrgen: fix RE generation
|
2012-02-18 18:56:18 +01:00 |
|
Sebastien Bourdeauducq
|
026457a98c
|
Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
|
2012-02-18 18:12:14 +01:00 |
|
Sebastien Bourdeauducq
|
55a265d967
|
bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |
|
Sebastien Bourdeauducq
|
92dfbb92dd
|
bus: add interconnect statements function
|
2012-02-17 23:51:32 +01:00 |
|
Sebastien Bourdeauducq
|
f995e8b92e
|
fhdl: check we pass BV to signals
|
2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
|
5bc840b9c1
|
DFI injector (untested)
|
2012-02-17 23:50:10 +01:00 |
|
Sebastien Bourdeauducq
|
c38de34a21
|
bios: DDR initialization skeleton
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2012-02-17 18:47:04 +01:00 |
|
Sebastien Bourdeauducq
|
e5927e265f
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bios: add flash target using m1nor
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2012-02-17 18:16:29 +01:00 |
|
Sebastien Bourdeauducq
|
48ddbf0c85
|
Add build Makefile and JTAG load script
|
2012-02-17 18:09:48 +01:00 |
|
Sebastien Bourdeauducq
|
c387ce7ce5
|
Map DDR PHY controls in CSR
|
2012-02-17 17:34:59 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
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fhdl/verilog: properly connect instance inouts
|
2012-02-17 11:08:41 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
cdd58e023b
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s6ddrphy: use single-ended DQS
|
2012-02-17 10:53:58 +01:00 |
|
Sebastien Bourdeauducq
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cc5e4ae710
|
clkfx: remove
|
2012-02-16 19:30:00 +01:00 |
|
Sebastien Bourdeauducq
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204452b0d3
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m1crg: make clock feedback pin bidirectional
|
2012-02-16 18:35:44 +01:00 |
|
Sebastien Bourdeauducq
|
f36a45edcb
|
lm32: compatibility with the new instance API
|
2012-02-16 18:35:22 +01:00 |
|
Sebastien Bourdeauducq
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ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
|
2012-02-16 18:02:37 +01:00 |
|
Sebastien Bourdeauducq
|
c08687b9c6
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bus/dfi: filter signals by direction
|
2012-02-15 21:48:05 +01:00 |
|
Sebastien Bourdeauducq
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ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
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fa9cf3e466
|
bus: add DFI
|
2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
|
859c9d8849
|
Use new bus API
|
2012-02-15 16:55:13 +01:00 |
|
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
|
af5230c8ee
|
bus: fix simple interconnect
|
2012-02-15 16:42:05 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
|
1368b666df
|
s6ddrphy: prepare quilt
|
2012-02-14 15:52:39 +01:00 |
|
Sebastien Bourdeauducq
|
b157d84434
|
README
|
2012-02-14 15:43:09 +01:00 |
|
Sebastien Bourdeauducq
|
46b1f74e98
|
bus/asmibus/hub: forward data and tag_call
|
2012-02-14 14:00:17 +01:00 |
|
Sebastien Bourdeauducq
|
aef2e4b5e8
|
Use double quotes for all strings
|
2012-02-14 13:15:00 +01:00 |
|
Sebastien Bourdeauducq
|
0c214b484e
|
Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
|
Sebastien Bourdeauducq
|
5165ff7ec3
|
Include Wishbone to ASMI bridge
|
2012-02-13 23:12:57 +01:00 |
|
Sebastien Bourdeauducq
|
e11d9b9322
|
bus/wishbone2asmi: cache hits working
|
2012-02-13 23:11:16 +01:00 |
|
Sebastien Bourdeauducq
|
1662e1b3bc
|
corelogic: support reverse in displacer/chooser
|
2012-02-13 23:10:27 +01:00 |
|
Sebastien Bourdeauducq
|
264be80f2d
|
Fix syntax errors and other stupid problems
|
2012-02-13 22:28:02 +01:00 |
|
Sebastien Bourdeauducq
|
8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
|
2012-02-13 21:46:39 +01:00 |
|
Sebastien Bourdeauducq
|
d6da88d11d
|
doc: update ASMI description
|
2012-02-13 17:23:32 +01:00 |
|
Sebastien Bourdeauducq
|
060426cb59
|
bus/wishbone2asmi: set WM, and send 0 when inactive
|
2012-02-13 16:49:43 +01:00 |
|
Sebastien Bourdeauducq
|
cad9d3b960
|
bus: Wishbone to ASMI caching bridge (untested)
|
2012-02-13 16:29:38 +01:00 |
|
Sebastien Bourdeauducq
|
244bf17db7
|
corelogic/misc: displacer + chooser
|
2012-02-11 20:57:08 +01:00 |
|
Sebastien Bourdeauducq
|
e10e4360f3
|
corelogic/misc/multimux: less confusing variable name
|
2012-02-11 20:56:51 +01:00 |
|
Sebastien Bourdeauducq
|
7894411418
|
bus/asmibus: fix typo
|
2012-02-11 20:56:01 +01:00 |
|
Sebastien Bourdeauducq
|
28b0c340af
|
corelogic/record: add to_signal convenience function
|
2012-02-11 20:55:23 +01:00 |
|
Sebastien Bourdeauducq
|
e62ac1d3a1
|
corelogic/misc: contiguous split
|
2012-02-11 11:52:15 +01:00 |
|
Sebastien Bourdeauducq
|
ef436a1ec9
|
bus/asmibus: add get_slots, fix get_fragment
|
2012-02-10 17:49:06 +01:00 |
|
Sebastien Bourdeauducq
|
945d655d45
|
bus: ASMI hub (untested)
|
2012-02-10 15:21:04 +01:00 |
|
Sebastien Bourdeauducq
|
c1bff38861
|
doc: update Bank description
|
2012-02-08 19:26:56 +01:00 |
|
Sebastien Bourdeauducq
|
0654bf4583
|
tools: use install and /usr/local (as suggested by David Kuehling)
|
2012-02-08 15:09:07 +01:00 |
|
Sebastien Bourdeauducq
|
bfd2bf4ed3
|
tools: remove bin2hex
|
2012-02-08 15:08:03 +01:00 |
|
Sebastien Bourdeauducq
|
755079d7fa
|
libbase: blocking UART write if IRQs are enabled
|
2012-02-07 15:12:27 +01:00 |
|
Sebastien Bourdeauducq
|
73fce59631
|
software: shell from original BIOS
|
2012-02-07 15:02:44 +01:00 |