Sebastien Bourdeauducq
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6d71e09281
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cif: move to milkymist folder
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2013-05-30 21:38:21 +02:00 |
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Sebastien Bourdeauducq
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fb3e61230b
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Use new memory port API
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2013-05-28 15:56:14 +02:00 |
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Sebastien Bourdeauducq
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611c4192b1
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Use migen.fhdl.std
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2013-05-22 17:10:13 +02:00 |
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Sebastien Bourdeauducq
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71cc2db867
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Add GPIO buttons and LEDs
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2013-05-16 17:43:20 +02:00 |
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Sebastien Bourdeauducq
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32c478af16
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top: integrate ADC for pots
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2013-05-13 15:45:06 +02:00 |
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Sebastien Bourdeauducq
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534dec62eb
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First video mixing working (hacky)
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2013-05-12 15:58:08 +02:00 |
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Sebastien Bourdeauducq
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e96b027dee
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Framebuffer mixing
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2013-05-10 21:03:55 +02:00 |
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Sebastien Bourdeauducq
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66b4bae7c8
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top: connect dvisampler DMA IRQs
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2013-05-08 22:31:42 +02:00 |
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Sebastien Bourdeauducq
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e2d15b169a
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dvisampler: mostly working, very basic and slightly buggy DMA
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2013-05-06 09:58:12 +02:00 |
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Sebastien Bourdeauducq
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4dcec32010
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top: allocate one more ASMI port to framebuffer
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2013-03-28 20:46:00 +01:00 |
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Sebastien Bourdeauducq
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8fd092ca12
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crg: support VGA pixel clock reprogramming
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2013-03-28 19:07:17 +01:00 |
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Sebastien Bourdeauducq
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1e860c7472
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Use new Mibuild generic_platform API
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2013-03-26 17:57:17 +01:00 |
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Sebastien Bourdeauducq
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fdf7f10f54
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Automatically build CSR access functions
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2013-03-25 14:42:48 +01:00 |
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Sebastien Bourdeauducq
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eaef3464e9
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Instantiate DVI sampler core for both ports
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2013-03-13 19:56:56 +01:00 |
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Sebastien Bourdeauducq
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a9b723568a
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Use new module, autoreg and eventmanager Migen APIs
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2013-03-10 19:32:38 +01:00 |
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Sebastien Bourdeauducq
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5649e88a90
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Use Mibuild
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2013-02-11 18:23:06 +01:00 |
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Sebastien Bourdeauducq
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0392dd8ac2
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bank/csrgen: interface -> bus
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2012-12-06 17:15:47 +01:00 |
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Sebastien Bourdeauducq
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fee70e9866
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Use Wishbone SRAM component from Migen
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2012-12-01 12:59:32 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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c86dd3cbef
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Define clock domains instead of passing extra clocks as regular signals
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2012-09-11 00:21:07 +02:00 |
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Sebastien Bourdeauducq
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5931c5eb59
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Basic support for new clock domain and instance API
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2012-09-10 23:47:06 +02:00 |
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Sebastien Bourdeauducq
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855eec776d
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Add ASMIprobe core
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2012-08-04 16:31:24 +02:00 |
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Sebastien Bourdeauducq
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6073f68b69
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asmicon: simple selector option
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2012-07-13 19:25:38 +02:00 |
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Sebastien Bourdeauducq
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b7aec21a47
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top: use two slots for the framebuffer ASMI port
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2012-07-12 19:40:49 +02:00 |
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Sebastien Bourdeauducq
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a52c3135c1
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framebuffer: frame initiator
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2012-06-17 17:22:02 +02:00 |
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Sebastien Bourdeauducq
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3a02524cc7
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VGA framebuffer connections
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2012-06-17 13:41:26 +02:00 |
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Sebastien Bourdeauducq
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f6f42293d1
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Clock frequency detection
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2012-05-22 13:23:44 +02:00 |
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Sebastien Bourdeauducq
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c01594f9fd
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Common interrupt numbers
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2012-05-21 19:52:41 +02:00 |
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Sebastien Bourdeauducq
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94245517f2
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Add timer
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2012-05-21 19:46:04 +02:00 |
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Sebastien Bourdeauducq
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8ad251c94c
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Connect Ethernet IRQ
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2012-05-20 23:48:41 +02:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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79124d822b
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Identifier
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2012-05-17 01:41:41 +02:00 |
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Sebastien Bourdeauducq
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141269b384
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Get CSR base addresses from include file
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2012-05-16 10:36:46 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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c26efa28ca
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asmicon: multiplexer (untested)
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2012-03-18 22:11:01 +01:00 |
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Sebastien Bourdeauducq
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0e00837f42
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asmicon: move slot time to timing settings
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2012-03-18 14:57:31 +01:00 |
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Sebastien Bourdeauducq
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b1eb919ad2
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asmicon: bank machine (untested)
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2012-03-18 00:12:03 +01:00 |
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Sebastien Bourdeauducq
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7c377880fa
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asmicon: refresher (untested)
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2012-03-15 20:29:26 +01:00 |
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Sebastien Bourdeauducq
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7b14e0bd05
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asmicon: skeleton
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2012-03-14 18:26:05 +01:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
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5bc840b9c1
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DFI injector (untested)
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2012-02-17 23:50:10 +01:00 |
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Sebastien Bourdeauducq
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c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
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5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
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2012-02-17 11:04:44 +01:00 |
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Sebastien Bourdeauducq
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72f9af9d90
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Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
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Sebastien Bourdeauducq
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5165ff7ec3
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Include Wishbone to ASMI bridge
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2012-02-13 23:12:57 +01:00 |
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Sebastien Bourdeauducq
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58f4f78d2c
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sram: fix sub-word write
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2012-02-06 23:13:35 +01:00 |
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Sebastien Bourdeauducq
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33f1c456bf
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top: connect UART IRQ
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2012-02-06 17:45:40 +01:00 |
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Sebastien Bourdeauducq
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9b9a510525
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Memory map
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2012-02-05 19:54:08 +01:00 |