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720 commits

Author SHA1 Message Date
Sebastien Bourdeauducq
ccc9a0d334 test/test_size: fix slice comparison 2014-11-03 12:08:43 +08:00
Sebastien Bourdeauducq
dcedc4e6a5 actorlib/structuring/Pipeline: make 'busy' a signal 2014-11-01 21:48:02 +08:00
Florent Kermarrec
33c3a927c2 actorlib/structuring: add Pipeline 
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
 2014-11-01 21:47:00 +08:00
Florent Kermarrec
8db549a23d actorlib/structuring: add Converter 
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
 2014-11-01 21:43:52 +08:00
Sebastien Bourdeauducq
a7e4907724 Merge branch 'master' of github.com:m-labs/migen 2014-11-01 21:33:35 +08:00
Florent Kermarrec
bd1d456f5d flow/actor, actorlib/structuring: add packet support 2014-11-01 21:22:46 +08:00
Florent Kermarrec
4d1b6da42f bus/csr: add configurable address_width (needed more than 32 modules with CSR) 2014-11-01 21:22:11 +08:00
Florent Kermarrec
fcf2f7517c crc: generate error asynchronously to avoid stalling the flow and simplify 2014-11-01 21:21:46 +08:00
Sebastien Bourdeauducq
a4782899f6 fhdl/verilog: fix tristate to instance connection 2014-10-29 18:18:17 +08:00
Yann Sionneau
286092b62e Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
Florent Kermarrec
86abb253c8 flow/actor/Endpoint: clean up __getattr__ 2014-10-22 09:35:30 +08:00
Florent Kermarrec
37031e3a2f DMAWriteController: fix Demultiplexer layout 2014-10-20 23:58:16 +08:00
Florent Kermarrec
07c33279c2 use new direct access on endpoints 2014-10-20 23:12:16 +08:00
Florent Kermarrec
ff688fb2f9 _Endpoint: allow direct access of payload elements 2014-10-20 23:09:56 +08:00
Florent Kermarrec
dbaeaf7833 remove trailing whitespaces 2014-10-17 17:08:46 +08:00
Florent Kermarrec
22507b117c bank: add re to CSRStorage 
being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
 2014-10-16 17:43:41 +08:00
Sebastien Bourdeauducq
15f67b30d0 genlib/fsm: make first fsm.act() the reset state, even when using after_*/before_* methods before fsm.act 2014-09-29 19:38:58 +08:00
Florent Kermarrec
e03091e7e2 add generic CRCEngine, CRC32, CRCInserter and CRCChecker 
CRCEngine implements a generic and optimized CRC LFSR. It will enable generation of CRC generators and checkers.
CRC32 is an implementation of IEEE 802.3 CRC using the CRCEngine.
CRC32Inserter and CRC32Checker have been tested on an ethernet MAC.
 2014-09-26 11:42:10 +08:00
Florent Kermarrec
a03570ccca flow/actor: fix eop direction 2014-09-23 00:14:58 +08:00
Florent Kermarrec
66054af7bb flow/actor: add packetized parameter for Sink and Source 2014-09-22 23:45:28 +08:00
Florent Kermarrec
967b73bef3 actorlib/structuring: add reverse parameter to Unpack and Pack 2014-09-22 23:41:40 +08:00
Sebastien Bourdeauducq
6c9810532b genlib/fifo/SyncFIFOBuffered: replace not supported 2014-09-17 19:59:13 +08:00
Sebastien Bourdeauducq
4cacf97088 genlib/fifo: same 'level' semantics between SyncFIFOBuffered and FWFT SyncFIFO 2014-09-17 19:58:43 +08:00
Sebastien Bourdeauducq
264bc61e04 genlib/fifo: add replace command to sync FIFO 2014-09-10 21:19:15 +08:00
Sebastien Bourdeauducq
325ffdc6c6 actorlib/spi: remove unneeded import 2014-09-08 18:48:54 +08:00
Florent Kermarrec
c1e12c3346 actorlib/spi: remove EventManager from DMAController 2014-09-08 11:34:21 +08:00
Robert Jordens
0bac463780 sim/icarus: add vpi directory to module search path 
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
 2014-09-07 16:49:12 +08:00
Robert Jordens
3d84a7a9de cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic 2014-09-07 16:49:12 +08:00
Robert Jordens
11f58862db test_cordic: stop spewing out numbers 2014-09-07 16:49:12 +08:00
Robert Jordens
4def6ec391 flow/network: replace NetworkX MultiDiGraph with simple implementation 2014-09-07 16:48:46 +08:00
Robert Jordens
683643266f cordic: vivado is bad at inferring compact adder/subtractor logic 2014-09-04 15:25:34 +08:00
Robert Jordens
bd232f3f61 fhdl.structure: do not permit clock domain names that start with numbers 2014-08-18 11:01:56 +08:00
Robert Jordens
ac2e961618 fhdl.structure: remove unused imports 2014-08-18 11:01:56 +08:00
Robert Jordens
6036fffef2 Signal.__getitem__: raise TypeError and IndexError when appropriate 2014-08-18 11:01:56 +08:00
Robert Jordens
b3d69913cd Signal.like: pass kwargs 2014-08-18 11:01:56 +08:00
Sebastien Bourdeauducq
60706e4b70 bus/dfi: add CKE and RESET_N 2014-08-09 10:56:08 +08:00
Sebastien Bourdeauducq
b124a98d92 genlib: add reset synchronizer 2014-08-06 19:38:37 +08:00
Sebastien Bourdeauducq
8baa957539 genlib/fifo: use synchronous memory read instead of additional register 
The latter causes problems with InsertReset
 2014-08-02 08:52:49 +08:00
Robert Jordens
44c6e524ba migen.fhdl.structure: add Signal.like(other) 
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
 2014-07-24 23:52:59 -06:00
Florent Kermarrec
9fcea6e64a migen/sim/generic: use kwargs to pass parameters to icarus.Runner 2014-07-24 10:17:54 -06:00
Robert Jordens
10d639d313 flow.plumbing: spelling 2014-07-19 14:29:51 -06:00
Robert Jordens
9266e10cae flow.plumbing: make argument order consistent 2014-07-19 14:29:50 -06:00
Sebastien Bourdeauducq
ff1d105c7e genlib/SyncFIFO: remove flush signal (use InsertReset instead) 2014-07-17 19:15:45 -06:00
Florent Kermarrec
ea0f4706f5 fsm: set reset_state as default state 2014-06-22 15:21:22 +02:00
Florent Kermarrec
4c426b36f3 fifo: add support for depth=2 2014-06-15 23:58:46 +02:00
Florent Kermarrec
70a2ee4368 migen/bank/description: add reset parameter to CSRStatus 2014-06-15 23:54:38 +02:00
Florent Kermarrec
9c1d95f6a4 wishbone2lasmi: fix wordbits computation 2014-05-01 13:32:18 +02:00
Sebastien Bourdeauducq
29ed3918cc fhdl: forbid zero-length signals 2014-04-18 15:01:50 +02:00
Florent Kermarrec
86f852a5f1 wishbone2lasmi: support lasmim data_width < wishbone data_width 2014-04-18 15:00:53 +02:00
Sebastien Bourdeauducq
a36a208dd1 sim: use (mandatory) ncycles when starting a simulation with no active functions 2014-04-13 15:16:27 +02:00