5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
96c369f3e4
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
2019-10-11 21:55:26 +02:00
29e51f5e97
interconnect/wishbone: fix Converter case when buses are identical
2019-10-11 21:49:11 +02:00
ae9c25b74f
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
9a82933858
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
2019-10-11 09:01:50 +02:00
ca81cc209b
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
2019-10-11 09:01:08 +02:00
03faf06c82
soc/interconnect/axi: re-align to improve readability
2019-10-11 08:41:05 +02:00
7dea9afd7d
software/bios: simplify banners
2019-10-11 08:38:12 +02:00
6bd1889330
cpu/picorv32: remove obsolete comment
2019-10-10 22:29:54 +02:00
28517d20ca
cpu/picorv32: use a single idbus
2019-10-10 22:02:04 +02:00
5daf1a2296
cpu: cleanup/re-align
2019-10-10 21:52:09 +02:00
467d35edee
cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix
2019-10-10 21:40:29 +02:00
1045cda39e
cpu: add buses list and use it in soc_core to add bus masters
2019-10-10 21:35:06 +02:00
42ccc91f74
integration: move soc constants to soc.h of csr.h
...
software retro-compat with soc.h included in csr.h
2019-10-10 21:15:49 +02:00
ed3c53d7cd
build/generic_platform: only add sources if language is not None
2019-10-10 19:39:33 +02:00
f3ba078882
xilinx/vivado: replace "xy" == language with language == "xy"
2019-10-10 19:36:17 +02:00
17756f631b
Merge pull request #277 from railnova/feature/vivado_sysverilog_support
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[feature] Add SystemVerilog support for the Vivado builder
2019-10-10 19:31:09 +02:00
b25194826e
integration/soc_zynq: shadow_base no longer recommended (replace with io_regions)
2019-10-10 19:23:01 +02:00
496ba7e594
bios/main: use same banner than README (MiSoC cited in README/LICENSE)
2019-10-10 19:21:32 +02:00
840f01b6d5
software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf
2019-10-10 19:18:28 +02:00
f2369a4c9e
Add system Verilog support for the Vivado builder
2019-10-10 14:10:28 +02:00
37531cec81
Merge pull request #276 from gsomlo/gls-rocket-map
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cpu/rocket: swap main_mem and io regions
2019-10-09 21:25:57 +02:00
f8f643a02f
cpu/rocket: swap main_mem and io regions
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The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.
As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.
Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-09 14:25:41 -04:00
b627a8fe71
cpu: add default io_regions to CPUNone (all address range can be used as IO)
2019-10-09 12:06:21 +02:00
cc245fc8ec
Merge pull request #275 from pcotret/patch-1
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Update README (related to issue #273 )
2019-10-09 11:20:50 +02:00
a6b3aa3c62
soc_core: improve check_io_region error message
2019-10-09 10:47:19 +02:00
dc656d48c2
targets/sim: switch from shadow_base to io_regions
2019-10-09 10:38:22 +02:00
10146abf0a
cpu/rocket: move csr to IO region
2019-10-09 10:24:01 +02:00
7f1d4623ff
build/xilinx/vivado: fix default synth-mode
2019-10-09 10:19:18 +02:00
a4ef9b29b9
soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)
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The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.
The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length
It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.
2019-10-09 10:15:42 +02:00
e923a88dcc
Update README (related to issue #273 )
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Following my problems with the quick start guide (issue #273 ), I suggest a few modifications to have a "real" quick start guide.
2019-10-09 09:48:32 +02:00
e8b90e8009
Merge pull request #274 from gsomlo/gls-shadow-base
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builder: use the SoC's existing shadow base with get_csr_header()
2019-10-08 21:15:54 +02:00
53777391e8
builder: use the SoC's existing shadow base with get_csr_header()
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Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
2019-10-08 14:28:50 -04:00
92975b139e
targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys
2019-10-07 10:38:26 +02:00
4a1cefe946
build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode
2019-10-07 10:37:16 +02:00
3e22d4b9e6
xilinx/common: be sure language is not vhdl when yosys synthesis is used
2019-10-07 10:36:32 +02:00
975bd9be8b
cpu/vexriscv: use specific mem_map for linux variant
2019-10-07 08:50:03 +02:00
2dfe7441d6
Merge pull request #271 from gsomlo/gls-yosys-nowidelut
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RFC: optional '-nowidelut' flag for yosys synth_ecp5
2019-10-06 14:55:44 +02:00
6aa76b1df8
trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
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Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).
Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-06 08:37:43 -04:00
c954ff0cfa
Merge pull request #272 from sergachev/fix-comments
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fix comments in icap.py
2019-10-06 12:10:19 +02:00
2f7bd97129
fix comments
2019-10-06 10:47:28 +02:00
ab4a5d1dc1
litex_setup: add litejesd204b
2019-10-04 10:00:45 +02:00
960b25a541
Merge pull request #270 from gsomlo/gls-csr-upper
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soc/integration: ensure CSR constants are in uppercase
2019-10-01 21:40:56 +02:00
41ad08e8ef
soc/cores/icap: simplify ICAPBitstream (untested)
2019-10-01 21:30:14 +02:00
0c2993866c
soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP
2019-10-01 21:04:49 +02:00
4bb2827e05
Merge pull request #269 from antmicro/rework_icap
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soc: cores: support sending custom bitstream to ICAP
2019-10-01 20:55:28 +02:00
c8790d342a
soc/integration: ensure CSR constants are in uppercase
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Fixup over commit 8be5824e
2019-10-01 12:15:25 -04:00
4423a46ba2
soc: cores: support sending custom bitstream to ICAP
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This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
2019-10-01 13:44:45 +02:00
427d7af767
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
2019-09-30 23:41:07 +02:00
59bf04d965
soc/interconnect/stream: add separators, mode Actor modules just after Endpoint
2019-09-30 23:33:25 +02:00
Florent Kermarrec
Martin Cornil
Gabriel Somlo
Pascal Cotret
Ilia Sergachev
Jan Kowalewski