bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
746e452838
actorlib/dma_asmi: support for writes
2013-04-28 18:06:36 +02:00
6c08cd67aa
graycounter: expose binary output
2013-04-25 13:11:15 +02:00
0f9df2d732
genlib: add Gray counter
2013-04-24 19:13:36 +02:00
f599fe4ade
Support for resetless clock domains
2013-04-23 11:54:05 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
6a3c413717
New bidirectional-capable Record API
2013-04-01 21:53:33 +02:00
c4f4143591
New CSR API
2013-03-30 17:28:41 +01:00
b38818eb17
examples/sim/fir: convert to new API
2013-03-19 11:46:27 +01:00
af4eb02551
examples/basic/arrays: demonstrate lowering of Array in Instance expression
2013-03-18 18:37:23 +01:00
e2d156ef64
genlib/cdc/MultiReg: remove idomain
2013-03-15 19:49:24 +01:00
51bec340ab
sim: remove PureSimulable (superseded by Module)
2013-03-15 19:41:30 +01:00
208e039bbb
Local clock domain example
2013-03-15 18:18:32 +01:00
c99cc9343f
examples/pytholite: use new APIs
2013-03-12 16:59:24 +01:00
907bfa87f4
examples/basic: use new APIs
2013-03-12 16:45:28 +01:00
c2d54f481f
examples/psync: cleanup
2013-02-23 19:14:31 +01:00
6abac5907b
examples/basic/psync: demonstrate the new features
2013-02-23 19:04:11 +01:00
3a591c358c
examples/fir: better filter
2013-02-22 23:19:56 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
38664d6e16
fhdl: inline synthesis directive support
2013-02-22 19:10:02 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
dc93a231c6
fhdl: tristate support
2013-02-15 00:17:24 +01:00
92b67df41c
sim: default runner to Icarus Verilog
2013-02-09 17:04:53 +01:00
314a6c7743
corelogic: complex arithmetic support
2013-01-05 14:18:36 +01:00
4d0db2cb05
examples/pytholite: fix imports
2012-12-16 20:26:23 +01:00
a67f483f0f
Token: support idle_wait
2012-12-14 19:16:22 +01:00
6f99241585
Move Token to migen.flow.transactions
2012-12-14 15:55:38 +01:00
a7227d7d2b
Remove ActorNode
2012-12-12 22:20:48 +01:00
d8e478efee
Replace Signal(bits_for(... with Signal(max=...
2012-11-29 21:53:36 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
2a3ef28041
examples/sim/dataflow: update to new APIs
2012-11-28 22:44:14 +01:00
39d577d65e
examples/dataflow/dma: update to new APIs
2012-11-28 22:42:01 +01:00
7c4b5931bc
examples/basic: remove unroll example
2012-11-28 22:16:02 +01:00
5440fa715c
examples/basic/arrays: add array assignment to fragment
2012-11-26 22:47:35 +01:00
2418367c7a
examples/sim/memory: do not use MemoryPort
2012-11-26 18:19:10 +01:00
dac0d11e52
actorlib/sim: Dumper
2012-11-24 00:00:07 +01:00
784a399431
examples/memory: use new get_port API
2012-11-23 19:18:08 +01:00
7c6ebcf753
examples/pytholite/uio: demonstrate memories
2012-11-23 16:24:20 +01:00
20d87682ad
examples/pytholite/uio: simulate and convert Pytholite
2012-11-23 13:10:40 +01:00
89643bc434
sim/ipc/Message: convert values
2012-11-17 23:19:40 +01:00
6434ddd95a
examples/pytholite: add uio example
2012-11-17 22:26:14 +01:00
86090e1cbd
bus/asmibus: swap port position to be consistent with wishbone API
2012-11-17 19:42:39 +01:00
748741b49a
examples/pytholite/basic: demonstrate conversion to Verilog
2012-11-16 19:38:57 +01:00
7c7addbbe8
examples: basic Pytholite demo
2012-11-16 19:34:34 +01:00
daee4fb58c
transform/unroll_sync: autodetect in/out
2012-10-15 20:32:07 +02:00
eacba52fba
transform/unroll: support for variables
2012-10-12 19:54:03 +02:00
e5fc9cc675
transform: unroll
2012-10-12 13:16:39 +02:00
Sebastien Bourdeauducq
Florent Kermarrec