Sebastien Bourdeauducq
|
d0676e2dd1
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migen/fhdl/autofragment: factorize
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2013-03-09 23:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
d0d2df3c4b
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fhdl/autofragment: remove legacy functions
|
2013-03-09 23:05:45 +01:00 |
|
Sebastien Bourdeauducq
|
72fb6fd6bd
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fhdl/tools/flat_iteration: generalize
|
2013-03-09 23:03:15 +01:00 |
|
Sebastien Bourdeauducq
|
f53acb92e7
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fhdl/autofragment: fix submodules
|
2013-03-09 21:15:38 +01:00 |
|
Sebastien Bourdeauducq
|
6da8eb906f
|
fhdl/autofragment: empty build_fragment by default
|
2013-03-09 19:10:47 +01:00 |
|
Sebastien Bourdeauducq
|
2b8dc52c13
|
Use common definition for FinalizeError
|
2013-03-09 19:03:13 +01:00 |
|
Sebastien Bourdeauducq
|
6fa30053bf
|
fhdl/verilog: tristate outputs are always wire
|
2013-03-06 11:30:52 +01:00 |
|
Sebastien Bourdeauducq
|
bb5ee8d3bd
|
fhdl/autofragment: bugfixes + add auto_attr
|
2013-03-03 17:53:06 +01:00 |
|
Sebastien Bourdeauducq
|
cc8118d35c
|
fhdl/autofragment: FModule
|
2013-03-02 23:30:54 +01:00 |
|
Sebastien Bourdeauducq
|
c10622f5e2
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fhdl/verilog: insert reset before listing signals
|
2013-02-27 18:10:04 +01:00 |
|
Sebastien Bourdeauducq
|
a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
1b18194b1d
|
fhdl: TSTriple
|
2013-02-19 17:26:02 +01:00 |
|
Sebastien Bourdeauducq
|
dc93a231c6
|
fhdl: tristate support
|
2013-02-15 00:17:24 +01:00 |
|
Sebastien Bourdeauducq
|
63d399b6ad
|
fhdl/autofragment: from_attributes
|
2013-02-11 18:34:01 +01:00 |
|
Sebastien Bourdeauducq
|
473fd20f8c
|
fhdl/structure: store clock domain name
|
2013-01-24 13:49:49 +01:00 |
|
Sebastien Bourdeauducq
|
3201554f76
|
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
|
2013-01-23 15:13:06 +01:00 |
|
Sebastien Bourdeauducq
|
badba89686
|
fhdl: support nested statement lists
|
2013-01-05 14:18:15 +01:00 |
|
Sebastien Bourdeauducq
|
3fae6c8f03
|
Do not use super()
|
2012-12-18 14:54:33 +01:00 |
|
Sebastien Bourdeauducq
|
b06fbdedd6
|
fhdl/tools: bitreverse
|
2012-12-14 23:56:16 +01:00 |
|
Sebastien Bourdeauducq
|
483b821342
|
fhdl/structure: do not create Signal in Instance when parameter is int
|
2012-12-06 20:56:46 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
|
Fix various errors from new bitwidth/signedness system conversion
|
2012-11-29 23:36:55 +01:00 |
|
Sebastien Bourdeauducq
|
261166d92b
|
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
|
2012-11-29 22:59:54 +01:00 |
|
Sebastien Bourdeauducq
|
55d143a454
|
fhdl/structure: add unary minus
|
2012-11-29 22:52:57 +01:00 |
|
Sebastien Bourdeauducq
|
50ed73c937
|
New specification for width and signedness
|
2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
|
59831e0485
|
fhdl/structure: improved bits_for function
|
2012-11-28 18:39:44 +01:00 |
|
Sebastien Bourdeauducq
|
11b1e53224
|
visit/NodeTransformer: copy most nodes
|
2012-11-28 17:50:55 +01:00 |
|
Sebastien Bourdeauducq
|
a2bcbfdf8f
|
fhdl/tools: use NodeTransformer to lower arrays
|
2012-11-28 17:46:15 +01:00 |
|
Sebastien Bourdeauducq
|
3bc15024ac
|
fhdl/tools: use NodeVisitor
|
2012-11-26 21:40:23 +01:00 |
|
Sebastien Bourdeauducq
|
1460f069f6
|
fhdl/structure: remove deprecated MemoryPort
|
2012-11-26 19:36:43 +01:00 |
|
Sebastien Bourdeauducq
|
27d87c9412
|
fhdl/structure: disable we_granularity when larger than width
|
2012-11-23 23:08:12 +01:00 |
|
Sebastien Bourdeauducq
|
f42683b71e
|
fhdl/structure/Memory: fix we width
|
2012-11-23 19:21:52 +01:00 |
|
Sebastien Bourdeauducq
|
0f6215a13a
|
fhdl/structure: add Memory.get_port API
|
2012-11-23 19:17:49 +01:00 |
|
Sebastien Bourdeauducq
|
9d3e218863
|
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
|
2012-11-23 18:38:03 +01:00 |
|
Sebastien Bourdeauducq
|
3971600917
|
fhdl/structure: use sets for memories and instance collections
|
2012-11-23 17:20:08 +01:00 |
|
Sebastien Bourdeauducq
|
51e2e6ecd0
|
fhdl/verilog: remove empty cases
|
2012-11-18 16:32:51 +01:00 |
|
Sebastien Bourdeauducq
|
26cf1b8840
|
fhdl: make constants hashable
|
2012-11-09 20:17:43 +01:00 |
|
Sebastien Bourdeauducq
|
7744655ef2
|
fhdl/visit: add missing self
|
2012-11-09 17:37:24 +01:00 |
|
Sebastien Bourdeauducq
|
13af0ce556
|
fhdl: visit module (untested)
|
2012-11-09 16:00:11 +01:00 |
|
Sebastien Bourdeauducq
|
56d4cdeb48
|
fhdl/structure: make all values hashable
|
2012-11-06 13:51:51 +01:00 |
|
Sebastien Bourdeauducq
|
8101b68965
|
fhdl: fix instance get_io
|
2012-09-28 18:02:03 +02:00 |
|
Sebastien Bourdeauducq
|
c273866b08
|
fhdl: support expressions in instance ports
|
2012-09-22 20:51:10 +02:00 |
|
Sebastien Bourdeauducq
|
2fc9cae88a
|
fhdl: support inverted clock ports in instances
|
2012-09-22 20:50:49 +02:00 |
|
Sebastien Bourdeauducq
|
2e14569b5c
|
fhdl/verilog: sort clock domains by name
|
2012-09-11 10:00:03 +02:00 |
|
Sebastien Bourdeauducq
|
9a18a9df3f
|
fhdl: list signals in execution order
|
2012-09-11 09:59:37 +02:00 |