Commit Graph

132 Commits

Author SHA1 Message Date
Florent Kermarrec 2f7206b386 sdram: revert use of scalar values for DFIInjector 2015-03-03 09:09:54 +01:00
Florent Kermarrec 9df60bf98e lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True) 2015-03-03 09:02:53 +01:00
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
Sebastien Bourdeauducq 8e48502d03 spiflash: style 2015-03-03 00:54:30 +00:00
Florent Kermarrec 410a162841 sdram: disable by default bandwidth_measurement on lasmicon 2015-03-02 19:53:16 +01:00
Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
Florent Kermarrec 8280acd3a7 sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core 2015-03-02 12:17:49 +01:00
Florent Kermarrec 3465db25a7 soc/sdram: be more generic in naming 2015-03-02 11:55:28 +01:00
Florent Kermarrec 97331153e0 sdram: create core dir and move lasmicon/minicon in it 2015-03-02 11:38:22 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Florent Kermarrec 6b24562eea sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
Florent Kermarrec 46020fd253 sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look) 2015-03-02 10:34:29 +01:00
Florent Kermarrec c0b38e4905 sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus 2015-03-02 09:18:32 +01:00
Florent Kermarrec 7300879b7f sdram: move dfii to phy 2015-03-02 09:08:28 +01:00
Florent Kermarrec 9ad05b21ca sdram: fix remaining data_valid in dma_lasmi 2015-03-02 09:05:18 +01:00
Florent Kermarrec 88e7fa21e4 sdram: create test dir and move lasmicon/minicon tests to it 2015-03-02 08:42:55 +01:00
Florent Kermarrec b305b7828a sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
Florent Kermarrec 6d83a112e6 lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks) 2015-03-01 22:04:27 +01:00
Florent Kermarrec 4f37d29d05 flash/spi: make bitbang optional (enabled by default) 2015-03-01 17:15:22 +01:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec 9e01bf5fdd litesata: create example design derived from SoC 2015-03-01 11:33:38 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec 7b464b2b1c litesata: create specialized kc705 platform to avoid duplicating things already in mibuild 2015-03-01 11:03:15 +01:00
Florent Kermarrec b34be816ec liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 8e67d6e69f liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
Florent Kermarrec 0dfca49e68 litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
Florent Kermarrec b6358be0a1 merge litesata 2015-02-28 10:48:08 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00