Commit Graph

1735 Commits

Author SHA1 Message Date
Florent Kermarrec 651e228e22 litescope: pep8 (E401) 2015-04-13 13:28:47 +02:00
Florent Kermarrec 49dcf8d831 litescope: pep8 (E203) 2015-04-13 13:25:27 +02:00
Florent Kermarrec 51ca259bdb litescope: pep8 (E231) 2015-04-13 13:23:48 +02:00
Florent Kermarrec 67b4da8ecf litescope: pep8 (E201) 2015-04-13 13:20:13 +02:00
Florent Kermarrec 13e4d7c525 litescope: pep8 (E302) 2015-04-13 13:18:21 +02:00
Florent Kermarrec 1328328540 litescope: pep8 (replace tabs with spaces) 2015-04-13 13:09:44 +02:00
Florent Kermarrec 2bd38f44a3 liteeth: more pep8 (when convenient), should be almost OK 2015-04-13 13:02:04 +02:00
Florent Kermarrec 154d3d3b04 liteeth: pep8 (E265) 2015-04-13 11:27:01 +02:00
Florent Kermarrec 45dc4920ec liteeth: pep8 (E261, E271) 2015-04-13 11:07:50 +02:00
Florent Kermarrec 021a5ae8a0 liteeth: pep8 (W292) 2015-04-13 10:58:45 +02:00
Florent Kermarrec a84f12618b liteeth: pep8 (E225) 2015-04-13 10:56:18 +02:00
Florent Kermarrec 66ce40d880 liteeth: pep8 (E222) 2015-04-13 10:48:59 +02:00
Florent Kermarrec ff2d7f9adc liteeth: pep8 (E401) 2015-04-13 10:45:09 +02:00
Florent Kermarrec 726fd3ab42 liteeth: pep8 (E203) 2015-04-13 10:39:46 +02:00
Florent Kermarrec 8dc817dd70 liteeth: pep8 (E231) 2015-04-13 10:31:18 +02:00
Florent Kermarrec 9c527742cb liteeth: pep8 (E201) 2015-04-13 10:23:33 +02:00
Florent Kermarrec 5720638d85 liteeth: pep8 (E302) 2015-04-13 10:20:02 +02:00
Florent Kermarrec cd43eaffc2 liteeth: pep8 (replace tabs with spaces) 2015-04-13 09:53:43 +02:00
Florent Kermarrec afa9b889ae liteeth/phy/gmii: fix clock generation for mii mode (clock_pads.tx is an input) 2015-04-12 22:15:45 +02:00
Florent Kermarrec 3710afe7fe microudp.c: add #ifdef on ethmode (bios generation for gmii or mii was broken) 2015-04-12 20:59:50 +02:00
Florent Kermarrec 8e639160e3 liteeth/phy/gmii_mii: add pads registers in RX 2015-04-12 20:43:01 +02:00
Florent Kermarrec 0c27708b0a liteeth/phy/gmii_mii: avoid doubling pads register on TX 2015-04-12 20:42:12 +02:00
Florent Kermarrec bc81d9d639 liteeth/phy/__init__.py: add more comments 2015-04-12 18:56:46 +02:00
Florent Kermarrec 4abe8e1d9e microudp: fix if ( 2015-04-12 18:52:35 +02:00
Florent Kermarrec 515398634f liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode 2015-04-12 18:42:52 +02:00
Florent Kermarrec 857bee8a00 liteeth/phy: add GMII/MII phy
for now swicth is manual, we will need a clk counter to allow software or logic to automatically switch between GMII and MII
2015-04-12 17:25:55 +02:00
Florent Kermarrec cfac3d9f5c liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter 2015-04-12 16:03:21 +02:00
Florent Kermarrec ddae41f2e4 liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter 2015-04-12 15:34:56 +02:00
Florent Kermarrec 8c722db54e liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII) 2015-04-12 14:43:35 +02:00
Florent Kermarrec 4329e3e1b9 liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705) 2015-04-12 14:28:17 +02:00
Florent Kermarrec 93ed3212f7 timer: revert prescaler (we will in fact use a software prescaler for uIP) 2015-04-10 18:57:06 +02:00
Florent Kermarrec 80ef7291c1 timer: add prescaler 2015-04-10 13:58:44 +02:00
Robert Jordens d6c19858fa s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE 2015-04-10 16:12:29 +08:00
Sebastien Bourdeauducq 603a4ef51e liteeth: adapt to new ModuleTransformer 2015-04-10 11:42:25 +08:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Sebastien Bourdeauducq 3a2b677f85 soc,cpuif: support user defined constants 2015-04-09 00:34:36 +08:00
Sebastien Bourdeauducq 8b41ab3a5f make: add target in build names 2015-04-06 23:53:04 +08:00
Sebastien Bourdeauducq 176b9240a9 soc: use new ModuleTransformer API 2015-04-06 23:52:34 +08:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
2015-04-04 19:17:24 +08:00
Florent Kermarrec 2583e975f0 soc/cpuif: fix CSR base generation for memories (name is already fullname) 2015-04-03 13:57:37 +02:00
Florent Kermarrec c9c11e7aa8 soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions 2015-04-03 12:45:32 +02:00
Sebastien Bourdeauducq 85b3cced22 use str.format 2015-04-03 17:43:46 +08:00
Sebastien Bourdeauducq c7361f1cdf software/common.mak: fix alignment in quiet output 2015-04-03 17:43:29 +08:00
Florent Kermarrec 0db6e1d624 soc/cpuif: fix get_csr_header when obj is Memory (thanks ccube) 2015-04-03 11:14:28 +02:00
Sebastien Bourdeauducq 875abdeb8d make.py: use os.path.join 2015-04-03 16:00:07 +08:00
Sebastien Bourdeauducq 73d3b8487c crt0-or1k: clean up indentation 2015-04-03 13:23:28 +08:00
Florent Kermarrec b437dc3185 remove use of _r prefix on CSRs 2015-04-02 12:18:43 +02:00
Sebastien Bourdeauducq 696819cc7f move gpio from cpu.peripherals to com 2015-04-02 17:17:33 +08:00
Sebastien Bourdeauducq 63f14f3f30 libbase: implement flush_l2_cache for or1k 2015-04-02 16:47:03 +08:00