Sebastien Bourdeauducq
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e4144f2c7d
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software/common.mak: use -target instead of deprecated -ccc-host-triple
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2013-01-10 17:13:33 +01:00 |
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Sebastien Bourdeauducq
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b0503aaf85
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software/include/base/stdint.h: more definitions
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2013-01-10 17:10:29 +01:00 |
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Sebastien Bourdeauducq
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314a6c7743
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corelogic: complex arithmetic support
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2013-01-05 14:18:36 +01:00 |
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Sebastien Bourdeauducq
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badba89686
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fhdl: support nested statement lists
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2013-01-05 14:18:15 +01:00 |
Florent Kermarrec
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e6042c122c
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adapt migScope to Migen changes
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2013-01-03 01:46:39 +01:00 |
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Sebastien Bourdeauducq
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47f5fc70e4
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pytholite: fix bug with constant assignment to register
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2012-12-19 16:21:57 +01:00 |
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Sebastien Bourdeauducq
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9c65402fda
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pytholite: prune unused registers
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2012-12-19 16:03:05 +01:00 |
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Sebastien Bourdeauducq
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51f4f920a2
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Do not use super()
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2012-12-18 14:55:58 +01:00 |
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Sebastien Bourdeauducq
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3fae6c8f03
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Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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4d0db2cb05
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examples/pytholite: fix imports
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2012-12-16 20:26:23 +01:00 |
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Sebastien Bourdeauducq
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b06fbdedd6
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fhdl/tools: bitreverse
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2012-12-14 23:56:16 +01:00 |
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Sebastien Bourdeauducq
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1f350adf14
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actorlib/sim/SimActor: do not drive busy low when generator yields None
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2012-12-14 23:56:03 +01:00 |
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Sebastien Bourdeauducq
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a67f483f0f
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Token: support idle_wait
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2012-12-14 19:16:22 +01:00 |
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Sebastien Bourdeauducq
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6f99241585
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Move Token to migen.flow.transactions
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2012-12-14 15:55:38 +01:00 |
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Sebastien Bourdeauducq
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c44ff8941c
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Move Token
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2012-12-14 15:54:16 +01:00 |
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Sebastien Bourdeauducq
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3986790621
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Remove ActorNode
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2012-12-12 22:52:55 +01:00 |
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Sebastien Bourdeauducq
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28b4d99d31
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replace some forgotten is_abstract()
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2012-12-12 22:36:45 +01:00 |
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Sebastien Bourdeauducq
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a7227d7d2b
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Remove ActorNode
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2012-12-12 22:20:48 +01:00 |
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Sebastien Bourdeauducq
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8163ed4828
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Merge branch 'master' of github.com:milkymist/migen
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2012-12-06 20:57:30 +01:00 |
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Sebastien Bourdeauducq
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053f8ed82c
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Fix instantiations
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2012-12-06 20:57:00 +01:00 |
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Sebastien Bourdeauducq
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483b821342
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fhdl/structure: do not create Signal in Instance when parameter is int
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2012-12-06 20:56:46 +01:00 |
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Sebastien Bourdeauducq
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280a87ea69
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elsewhere: do not create interface in default param
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2012-12-06 17:34:48 +01:00 |
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Sebastien Bourdeauducq
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62187aa23d
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migen/bank: do not create interface in default param
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2012-12-06 17:28:28 +01:00 |
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Sebastien Bourdeauducq
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c3fdf42825
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bus/csr: add SRAM
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2012-12-06 17:16:17 +01:00 |
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Sebastien Bourdeauducq
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0392dd8ac2
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bank/csrgen: interface -> bus
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2012-12-06 17:15:47 +01:00 |
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Sebastien Bourdeauducq
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e89c66bf14
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bank/csrgen: interface -> bus
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2012-12-06 17:15:34 +01:00 |
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Sebastien Bourdeauducq
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273d9d285b
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bank/description: define reset value of read signal
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2012-12-05 16:40:44 +01:00 |
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Sebastien Bourdeauducq
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34ce934809
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actorlib/sim: drive busy high until generator is finished
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2012-12-05 16:40:12 +01:00 |
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Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
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Sebastien Bourdeauducq
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bec02c4783
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Merge branch 'master' of github.com:milkymist/milkymist-ng
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2012-12-01 12:59:47 +01:00 |
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Sebastien Bourdeauducq
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fee70e9866
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Use Wishbone SRAM component from Migen
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2012-12-01 12:59:32 +01:00 |
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Sebastien Bourdeauducq
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523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
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Sebastien Bourdeauducq
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adb1565d7a
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pytholite: fix bit width of selection signal
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2012-11-30 17:07:32 +01:00 |
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Sebastien Bourdeauducq
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cfb23c442f
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pytholite: support signed registers
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2012-11-30 17:07:12 +01:00 |
Michael Walle
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7a1e4cb66b
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lm32: fix watchpoints
The wp_match_n vector is off by one. Which results in undefined states, at
least in simulation.
Signed-off-by: Michael Walle <michael@walle.cc>
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2012-11-30 15:22:40 +01:00 |
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Sebastien Bourdeauducq
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7093939309
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corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |
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Sebastien Bourdeauducq
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31c722f993
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corelogic/roundrobin: fix request width
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2012-11-29 23:47:08 +01:00 |
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Sebastien Bourdeauducq
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293a62dabe
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 23:41:51 +01:00 |
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Sebastien Bourdeauducq
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8bf6945dfd
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Use new bitwidth/signedness system
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2012-11-29 23:38:04 +01:00 |
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Sebastien Bourdeauducq
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70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
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d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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070652cc39
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pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |
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Sebastien Bourdeauducq
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7e2bc00c0a
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Remove Constant
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2012-11-28 23:18:53 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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79e5f24a65
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Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
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2012-11-28 22:49:22 +01:00 |
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Sebastien Bourdeauducq
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2a3ef28041
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examples/sim/dataflow: update to new APIs
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2012-11-28 22:44:14 +01:00 |