1b9bdbdce4
Merge pull request #2016 from Dolu1990/vexiiriscv
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Update VexiiRiscv
2024-07-18 11:27:20 +02:00
f687425cb1
Update VexiiRiscv
2024-07-18 11:26:13 +02:00
473784581d
Merge pull request #2011 from Dolu1990/vexiiriscv
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cpu: Vexii/Nax fmax / area improvements
2024-07-12 17:29:45 +02:00
9fa1b4c123
Update Nax/Vexii
2024-07-12 16:17:30 +02:00
aef5a2094e
soc/cores/video: Add additional color formats
2024-07-10 15:21:51 +02:00
22ff3ac42d
Merge branch 'master' into vexiiriscv
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# Conflicts:
# litex/soc/cores/cpu/vexiiriscv/core.py
2024-07-10 09:37:43 +02:00
1267ba8ae6
Update Nax/Vexii
2024-07-10 09:35:34 +02:00
e4e9bd2125
interconnect/axi/axi_lite: Add bursting property even if always False.
2024-07-09 17:02:54 +02:00
372ab25273
Merge branch 'nax64_irq' into vexiiriscv
2024-07-09 15:18:25 +02:00
549d23e4f7
build/efinix: Add default parameter values and fix other typos.
2024-07-09 10:04:03 +02:00
e6171e79db
build/efinix: Fix typos (thanks @AndrewD).
2024-07-09 10:00:21 +02:00
7de4f01aa8
Merge pull request #2009 from trabucayre/efinix_args_opts
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build/efinix: added argument to change synthesis options configurations
2024-07-08 17:01:28 +02:00
ec1528fb69
build/efinix: added argument to change synthesis options configurations
2024-07-08 15:59:30 +02:00
0db650ac6a
soc/interconnect/stream: Improve MonitorCounter timings (avoid reset, clearer logic).
2024-07-05 13:56:14 +02:00
3c2ddd1655
cores/can/ctu_can_fd: Remove pads.irq that was used as debug.
2024-07-05 09:34:36 +02:00
7ec35eb4c5
Merge pull request #2007 from enjoy-digital/ctu-can-fd
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Add initial CTU-CAN-FD core support.
2024-07-05 09:16:21 +02:00
d838a9ca73
Merge pull request #2006 from trabucayre/update_altera_build
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Update altera build
2024-07-04 13:04:15 +02:00
9fd63973aa
build/altera/quartus.py: added support for ips other than QSYS_FILE
2024-07-04 09:51:09 +02:00
7393c35264
build/altera/platform,quartus: allows user to select Analysis&Synthesis tool (quartus_map (default) or quartus_syn
2024-07-04 09:50:06 +02:00
b286fe5621
Merge pull request #2005 from VOGL-electronic/json2dts_zephyr_remove_configs
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litex_json2dts_zephyr.py: Remove unnessesary configs
2024-07-04 09:10:27 +02:00
d4d1a1bfd7
gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.
2024-07-03 21:44:31 +02:00
aac828b4cb
soc/add_etherbone: Update ethmac.
2024-07-02 17:10:32 +02:00
b285992fb1
litex_json2dts_zephyr.py: Remove unnessesary configs
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Remove all configs, that are enabled by default
in zephyr based on the devicetree.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-07-02 15:04:50 +02:00
2a83bce63e
cores/dma: Automatically call add_ctrl method in add_csr is ctrl are not present.
2024-07-01 18:22:41 +02:00
9c07b45f3c
soc/add_ethernet: Add 64-bit data_width support.
2024-06-27 09:35:28 +02:00
3dd3477ea2
Merge pull request #2004 from enjoy-digital/wishbone_dma_ctrl
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Wishbone DMA: Split add_csr() method in add_ctrl()/add_csr().
2024-06-26 18:46:01 +02:00
4b745f9eba
soc/cores/dma: Add default parameters to add_ctrl.
2024-06-26 17:57:47 +02:00
01a15e4bbf
soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic.
2024-06-26 16:13:45 +02:00
23a0d8fa2a
soc/cores/dma/WishboneDMAReader: Split add_csr() in add_ctrl() /add_csr() since in some case just want to control the module from signals/user logic.
2024-06-26 16:07:12 +02:00
06a26b7c9b
Merge pull request #2003 from enjoy-digital/liteeth_wishbone_tx_rx_buses
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integration/soc/add_ethernet: Use separates TX/RX buses/regions for e…
2024-06-25 19:05:49 +02:00
14a640302c
integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac.
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LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161 .
2024-06-25 17:39:26 +02:00
1ad0f828bb
soc/add_pcie: Make it more flexible to allow disabling DMA tables and passing msis mapping from user design.
2024-06-25 15:07:37 +02:00
462016a1d0
litex/tools/litex_json2dts_linux: Add initial CAN support.
2024-06-24 13:01:18 +02:00
71ff4eaadc
soc/cores/can: Switch to our fork of CTU-CAN-FD, remove debug signals and do a git clone if not present in execution directory.
2024-06-24 12:53:38 +02:00
bad64bcf6d
soc/cores: Add initial CTU-CAN-FD integration from 2021 work with recent updates/tests.
2024-06-24 12:27:17 +02:00
8afa36f24a
CHANGES.md: Update and add Issue/PR number.
2024-06-24 10:52:34 +02:00
a47dde6fbc
Merge pull request #1999 from FlyGoat/csr-re
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csr_bus: Honour re signal from the upstream bus
2024-06-24 10:36:48 +02:00
8e4f8781f7
Merge pull request #1996 from VOGL-electronic/litex_watchdog
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core: add watchdog feature
2024-06-24 10:32:48 +02:00
11537ec8cc
Merge pull request #2001 from rtucker85/master
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liblitespi: fix xor-used-as-pow bug
2024-06-24 09:05:34 +02:00
21674ee29c
Merge pull request #1998 from FlyGoat/ahb-fixes
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soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
2024-06-24 09:04:33 +02:00
fd5a01dd26
integration/soc: Cleanup #1997 .
2024-06-24 09:03:24 +02:00
5aad0d6aca
Merge pull request #1997 from FlyGoat/axi-id-fixes
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integration/soc: data_width_convert: Inherit more bus properties
2024-06-24 09:00:31 +02:00
a0763bf652
liblitespi: fix xor-used-as-pow bug
2024-06-24 16:37:36 +10:00
af3d2a29fc
csr_bus: Honour re signal from the upstream bus
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Currently CSR bus assumed that ~we means reading, that created
a problem that when for a CSR if reading has side effects and adr
parked unintentionally at that CSR, the reading side effect will be
triggered.
For SoCs, this happened when upstream bus issued a write transaction
with wishbone.sel, then on CSR bus it will be translated
as adr = addr, we = 0, which will be interpreted as a read to such
address, and trigger undesired side effect for such CSR.
Such upstream transaction will be generated by our bus width converter.
Given that we signal already presents in CSR Interface, the easiest way
to handle such situation is to generate re signal at bus bridges and
propagate it all the way down to the Interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 19:35:19 +01:00
9bdc22adfb
soc/integration/soc.py: Fix creation of AHB2Wishbone bridge
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Don't do bus_addressing_convert as it's being handled in AHB2Wishbone
logic.
Add addressing parameters for AHBInterface constructor as required
by soc code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-23 16:18:26 +01:00
22f9c063db
Merge pull request #1949 from alexey-morozov/master
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The case when AWVALID and WVALID are not asserted at the same cycle
2024-06-23 09:03:17 +02:00
3d530e0b59
integration/soc: data_width_convert: Inherit more bus properties
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For data_width converter we need to ensure that adapted interface
have same properties as it's parent interface, so that id and user
signals for AXI will be propagated properly from parent to adapted
interface.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-06-22 17:54:41 +01:00
dd01a87653
Merge pull request #1993 from FlyGoat/jtag-patch
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Expand litex_sim JTAG support to more CPUs
2024-06-22 14:34:50 +02:00
0559f3f033
core: add watchdog feature
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Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-21 17:13:03 +02:00
29bdf6805f
Merge pull request #1840 from motec-research/parser_set_defaults_improvements
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Parser set defaults improvements
2024-06-21 10:52:09 +02:00
enjoy-digital
Dolu1990
inc
Gwenhael Goavec-Merou
Fin Maaß
Richard Tucker
Jiaxun Yang