Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,866 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

9866 Commits

Author SHA1 Message Date
enjoy-digital f40f63ae29
Merge pull request #1995 from VOGL-electronic/soc_spi_master_int 
soc: add_spi_master: make spi_clk_freq an int
 2024-06-19 19:34:31 +02:00
Fin Maaß 447469b0aa soc: add_spi_master: make spi_clk_freq an int 
convert spi_clk_freq to an int. this way the constant is also an int.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-06-19 16:29:35 +02:00
Gwenhael Goavec-Merou d9854582c6 build/lattice/radiant: allows extra configuration (prj_set_strategy_value XX=YY) to be added at script creation time 2024-06-19 16:22:30 +02:00
enjoy-digital d6b0c84f9c
Merge pull request #1992 from motec-research/fix_MockCSRRegion_base 
integration/export: Fix MockCSRRegion base definition.
 2024-06-19 09:13:49 +02:00
enjoy-digital e6353c8898
Merge pull request #1991 from motec-research/add_json_excludes 
Add json excludes
 2024-06-19 09:12:22 +02:00
Florent Kermarrec 5a0fd6fb60 CHANGES.md: Update. 2024-06-19 09:07:22 +02:00
enjoy-digital 6fdf5a27d8
Merge pull request #1994 from trabucayre/zynqmp_peripheral_bus 
soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default
 2024-06-19 08:48:03 +02:00
Gwenhael Goavec-Merou 146617eae8 soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default 2024-06-18 22:14:24 +02:00
Gwenhael Goavec-Merou cc21c662ca soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default 2024-06-18 19:46:56 +02:00
Jiaxun Yang 50c8ef07b6
jtagremote: Implement ntrst pin 
ntrst pin is critical to some JTAG taps to put tap
into a known state.

Implement it in jtagremote testbench with corresponding
remote bitbang commands and hook it up in litex_sim.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-06-18 14:49:43 +01:00
Florent Kermarrec f46ef03f42 build/openfpgaloader: print command before executing it to ease debugging/manual tests. 2024-06-18 15:35:27 +02:00
Jiaxun Yang a8b3f36592
soc/cores/cpu: Implement add_jtag method 
Implement add_jtag method for naxriscv, vexiiriscv and vexriscv_smp,
which is the de facto way to add JTAG ports to pads on other CPUs.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-06-18 14:14:52 +01:00
Gwenhael Goavec-Merou 63d72a87e6 soc/cores/cpu/zynqmp/core.py: added CAN over EMIO support 2024-06-18 12:26:36 +02:00
Gwenhael Goavec-Merou 0d1d378966 soc/cores/cpu/zynqmp/core.py: added interrupts support 2024-06-18 10:59:42 +02:00
Andrew Dennison 0f7ea96812 build/parser: detect invalid defaults 2024-06-18 09:37:31 +10:00
Andrew Dennison 4730ee2288 build/parser: support set_default(cpu_type="xxx") 
Ensures args_fill() for new cpu_type is called, allowing for patterns
in a target file like:

    parser.set_defaults(cpu_type="vexriscv_smp")
    parser.set_defaults(cpu_variant="linux")
    parser.set_defaults(with_fpu=True)
 2024-06-18 09:37:31 +10:00
Andrew Dennison dad04eedef integration/export: Fix MockCSRRegion base definition. 
MockCSR are not related to csr_base
 2024-06-18 09:07:39 +10:00
Andrew Dennison 56c284e9bc soc/integraion/builder: exclude some constants in add_json() 
Interrupt numbers from a downstream soc are not relevant in the main SOC
so exclude them by default.
 2024-06-18 09:01:28 +10:00
Andrew Dennison 702761d789 soc/integraion/builder: fix variable names 
In _get_json_*() variable names were transposed in two places
resulting in confusing code with correct functionality.
 2024-06-18 09:01:28 +10:00
Gwenhael Goavec-Merou 485341a1cf soc/cores/cpu/zynq7000/core.py: fix missing CAN IO mode (security/nitpick) 2024-06-17 18:26:28 +02:00
Gwenhael Goavec-Merou fba7ce42ec soc/cores/cpu/zynq7000/core.py: PS CANx support with EMIO pads 2024-06-17 18:09:00 +02:00
Gwenhael Goavec-Merou 6c4a756655 soc/cores/cpu/zynq7000/core.py: added GPx tcl configuration 2024-06-17 17:18:24 +02:00
Gwenhael Goavec-Merou 1335d3cebc soc/cores/cpu/zynq7000/core.py: enable F2P interrupts 2024-06-17 16:35:26 +02:00
Gwenhael Goavec-Merou 45928a3ce1 soc/cores/cpu/zynq7000/core.py: delayed filling ps7_tcl with config at finalize time 2024-06-17 16:29:23 +02:00
JoyBed 3f095a260d Fix HP slave clock source and specify AXI version 
The absence of WID signal in AXI4 when compared to AXI3 can sometimes cause problems.
 2024-06-17 16:16:07 +02:00
Florent Kermarrec a899c23f65 soc/interconnect/packet: Add default values for HeaderField parameters. 2024-06-17 10:54:53 +02:00
Florent Kermarrec 81b70d1e37 soc/integration/builder: Only generate svd/memory.x export when specified (Since often not required and generation does not seems robust to all designs). 2024-06-14 14:58:06 +02:00
Florent Kermarrec 69008d7d5e software/libbase/isr.c: Fix regression. 2024-06-14 14:08:22 +02:00
Florent Kermarrec 8278ff6622 software/libbase/isr.c: Generalize irq_table/attach/detach to all CPUS to have a common approach. 2024-06-14 12:08:52 +02:00
Florent Kermarrec 45753a3cc2 software/libbase/isr.c: Move ISR handling in more logical order (RISC-V PLIC first). 2024-06-14 11:49:33 +02:00
Florent Kermarrec 38e060c354 software/libbase/isr.c: Cleanup code a bit. 2024-06-14 11:47:06 +02:00
Florent Kermarrec 6164a55c6b cpu/cva6: Switch to common PLIC handling code to make it similar to other PLIC based CPU and avoid code "duplication". 2024-06-14 11:26:43 +02:00
Florent Kermarrec b58186a99d build/vhd2v_converter: Add GHDL synth woraround. 2024-06-14 11:25:21 +02:00
Dolu1990 28d4aff10f vexii non coherent config write bandwidth improvment 2024-06-13 23:20:25 +02:00
Florent Kermarrec 3fa3532f16 cores/video: Add fifo_depth parameter to add_video_framebuffer and use new KILOBYTE to define depth. 2024-06-13 12:59:09 +02:00
Florent Kermarrec 491974c719 litex_json2dts_linux: Cleanup bootargs IP address generation. 2024-06-13 12:14:44 +02:00
Florent Kermarrec 02d6e9760a litex_json2dts_linux: Improve/rework RISC-V cpu_isa_base/cpu_isa_extentions and make it specific to RISC-V CPUs. 2024-06-13 11:55:54 +02:00
Florent Kermarrec 3e756ecbbe CHANGES.md: Update. 2024-06-13 10:15:22 +02:00
Florent Kermarrec fcf9b3b335 litex_json2dts_linux: Use new byte size definition from litex.gen.common. 2024-06-13 09:55:19 +02:00
Florent Kermarrec d782a0f8c6 litex/gen/common: Add short and long byte size definitions. 2024-06-13 09:54:20 +02:00
Florent Kermarrec abdf6d3ee7 soc/integration: Generate CPU_FAMILY config and use it to simplify litex_json2dts_linux.py. 2024-06-13 09:33:04 +02:00
Florent Kermarrec 962bd67431 litex_json2dts_linux: Rename ncpus to cpu_count (Consistency with other variables). 2024-06-13 09:12:41 +02:00
enjoy-digital 2ddf9bb4e5
Merge pull request #1985 from VOGL-electronic/add_spi_master 
soc.py: Add spi master and changes in litex_json2dts_zephyr.py for the spi drivers
 2024-06-13 09:01:48 +02:00
enjoy-digital 7306c3862e
Merge pull request #1984 from VOGL-electronic/json2renode_elf 
litex_json2renode.py: add option for elf bios file and correct vexriscv variants
 2024-06-13 09:00:25 +02:00
Dolu1990 2e4813d6ae Fix vexii axi3 2024-06-12 19:33:20 +02:00
Florent Kermarrec eb3aca2a46 build/vhd2v_converter: Make instance rename when multiple instance more robust. 2024-06-12 15:16:03 +02:00
Florent Kermarrec 8d8dd117b6 soc/integration/builder: Now generates exports by default to output_dir with default name unless explicitly specified. 2024-06-12 11:44:34 +02:00
Dolu1990 8bb10e1617 cpu/vexii: Add AXI3 support via --with-axi3 2024-06-12 11:25:18 +02:00
Gwenhael Goavec-Merou 6ed61e11bc
Merge pull request #1983 from Dolu1990/vexiiriscv 
linux dts: add vexii clint support
 2024-06-11 18:40:13 +02:00
Dolu1990 8c80a6c19c linux dts: rework "rocket" in cpu_name into cpu_name == "rocket" 2024-06-11 13:08:25 +02:00