de31103cce
platforms/minispartan6: add ftdi_fifo pins
2015-03-22 11:20:22 +01:00
200979fb81
platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz
2015-03-22 03:37:27 +01:00
7440ccd65b
mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working)
2015-03-21 20:27:11 +01:00
1d2e7e8390
mibuild/platforms/minispartan6: adapt to recent changes (able to build simple example)
2015-03-21 18:31:50 +01:00
78b4f313bf
mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25)
2015-03-21 18:28:09 +01:00
1a03c340c9
mibuild/platforms: review and fix small mistakes
2015-03-21 18:23:35 +01:00
3a38626556
mibuild/platforms: add minispartan6 (from Matt O'Gorman)
2015-03-21 18:22:26 +01:00
4fe888702d
pipistrello: switch is a button
2015-03-19 18:56:49 +01:00
47ea451315
pipistrello: compress and load bitstream at 6MHz
2015-03-19 18:48:45 +01:00
860b72c8b6
pipistrello: rename sdram->ddram
2015-03-19 18:48:22 +01:00
3aee58f484
mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented)
2015-03-18 18:54:22 +01:00
ea9c1b8e69
fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code"
...
This probably breaks simulation with Icarus Verilog (and others simulators?)
2015-03-18 14:59:22 +01:00
500e58ce7d
mibuild/platform/versa: fix clock_constraints
2015-03-17 15:25:10 +01:00
e07b7f632c
mibuild/lattice: use ODDRXD1 and new synthesis directive
2015-03-17 14:59:36 +01:00
022ac26c22
mibuild/lattice: add LatticeAsyncResetSynchronizer
2015-03-17 12:42:36 +01:00
c06ab82f13
mibuild/platforms/versa: add ethernet clock constraints
2015-03-17 12:04:00 +01:00
ba2aeb08be
mibuild/platforms/versa: add rst_n
2015-03-17 11:51:34 +01:00
6dd8d89c6c
mibuild/lattice: fix LatticeDDROutput
2015-03-17 09:40:25 +01:00
9adf3f02f2
fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code
...
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
2015-03-17 00:40:26 +01:00
b5a9909b08
mibuild/xilinx/common: add LatticeDDROutput
2015-03-16 22:57:18 +01:00
993059a59c
mibuild/xilinx/common: add XilinxDDROutput
2015-03-16 22:53:05 +01:00
b3b1209c62
mibuild/platforms: add ethernet to versa
2015-03-16 22:24:10 +01:00
fab0b0b161
mibuild/platforms: add user_dip_btn to versa
2015-03-16 22:11:15 +01:00
d6041879dd
mibuild/lattice: use new Toolchain/Platform architecture
2015-03-16 21:24:21 +01:00
e903b62af1
mibuild/altera: use new Toolchain/Platform architecture
2015-03-16 21:07:55 +01:00
f7bfa13144
mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton)
2015-03-16 19:02:34 +01:00
aef9275c99
mibuild/xilinx: export special_overrides dictionary
2015-03-14 10:45:11 +01:00
d34b7d7a6b
mibuild/xilinx: remove obsolete CRG_DS
2015-03-14 00:27:24 +01:00
6a979a8023
mibuild: sanitize default clock management
2015-03-14 00:10:08 +01:00
702d177c85
mibuild: get rid of Platform factory function, cleanup
2015-03-13 23:25:15 +01:00
ff266bc2ee
migen/genlib/io: add DifferentialOutput and Xilinx implementation
2015-03-12 19:30:57 +01:00
c8ba8cde8e
migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild
2015-03-12 18:38:53 +01:00
00e8616de2
mibuild/sim: clean up (thanks sb)
2015-03-10 16:41:52 +01:00
555c444da2
mibuild/sim/dut_tb: fix permissions
2015-03-10 11:06:55 +01:00
9d8f1cd61d
mibuild/sim: get serial dev from /tmp/simserial
2015-03-10 00:42:54 +01:00
70a3e8081c
mibuild/sim: add support for pty
2015-03-09 23:31:11 +01:00
aa609bee15
mibuild/sim: remove hack, the issue was in gateware (padding)
2015-03-09 20:57:20 +01:00
efc5f221d9
mibuild/sim: clean up and move eth struct to sim
2015-03-09 14:40:33 +01:00
a72c091bc2
mibuild/sim: regroup console_tb/ethernet_tb in dut_tb
2015-03-09 14:40:31 +01:00
e82b540a96
mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up
2015-03-09 13:30:21 +01:00
3e84c66ba9
vivado: permit resources without pins
...
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
2015-03-09 13:30:19 +01:00
e60a97534b
mibuild/sim: able to visualize arp requests with wireshark
...
now need to find why that is not responding...
2015-03-06 20:16:30 +01:00
a64acdfa65
mibuild/sim: able to send ethernet frame from sim to server.py
2015-03-06 12:49:56 +01:00
0029b87628
mibuild/sim: add ethernet pins to verilor.py
2015-03-06 12:20:17 +01:00
658d4d4c49
platforms/sim: add ethernet pins
2015-03-06 10:20:26 +01:00
3d7f9fd685
mibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-04 00:55:35 +01:00
2d6fbd7902
mibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 22:52:28 +01:00
f4b060f6fe
mibuild/sim: avoid updating end at each cycle (simulation speedup)
2015-03-03 18:01:14 +01:00
5ec26a49c3
mibuild/sim: simplify console_tb with sim struct
2015-03-03 17:57:58 +01:00
991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq