Florent Kermarrec
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0826811047
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etherbone: import core from Robert Jordens
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2015-01-28 00:10:26 +01:00 |
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Florent Kermarrec
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46c4841d68
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mac: import files from MiSoC
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2015-01-27 23:59:06 +01:00 |
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Florent Kermarrec
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a160b04d2f
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init repo
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2015-01-27 23:50:52 +01:00 |
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Florent Kermarrec
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9d6a3e7f2a
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doc: add skeleton
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2015-01-27 21:35:58 +01:00 |
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Florent Kermarrec
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0c907e5afa
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fill building parameters
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2015-01-27 20:24:14 +01:00 |
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Florent Kermarrec
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7f9174f83d
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add storage qualifier
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2015-01-27 20:14:07 +01:00 |
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Florent Kermarrec
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fc96b20225
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add optional subsampler
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2015-01-27 19:58:02 +01:00 |
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Florent Kermarrec
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70d7152cda
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core/storage: split LiteScopeRecorder in LiteScopeRecorderUnit and LiteScopeRecorder
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2015-01-27 11:34:59 +01:00 |
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Florent Kermarrec
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64d18796e0
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change CSR class names (do not expose XXYYCSR to user)
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2015-01-25 21:34:13 +01:00 |
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Florent Kermarrec
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a3dae5fc5c
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host/driver: simplify
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2015-01-25 16:13:06 +01:00 |
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Florent Kermarrec
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4472dac603
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simplify code and use Sink/Source instead of records
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2015-01-25 15:58:00 +01:00 |
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Florent Kermarrec
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6f7d85b95c
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host: remove cpuif (we use the one from MiSoC) and some clean up
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2015-01-23 16:45:04 +01:00 |
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Florent Kermarrec
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9a3e9f86cf
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simplify LiteScopeLA export (use vns from platform on atexit)
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2015-01-23 10:07:58 +01:00 |
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Florent Kermarrec
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261469814f
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add hack to generate verilog with AsyncResetSynchronizer (FIXME)
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2015-01-23 03:18:25 +01:00 |
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Florent Kermarrec
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fb7864c2b9
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add missings __init__.py
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2015-01-23 01:14:35 +01:00 |
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Florent Kermarrec
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d45991d6eb
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fix README
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2015-01-23 01:07:51 +01:00 |
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Florent Kermarrec
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ea48f44b90
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add LiteScopeLA example
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2015-01-23 00:46:24 +01:00 |
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Florent Kermarrec
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5c40ff02cb
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add LiteScopeIO example
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2015-01-23 00:15:42 +01:00 |
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Florent Kermarrec
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f35f93a7c5
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start refactoring and change name to LiteScope
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2015-01-23 00:02:53 +01:00 |
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Florent Kermarrec
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609f8f9abb
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revert submodules/specials/clock_domains syntax
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2015-01-22 14:00:50 +01:00 |
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Florent Kermarrec
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fadac0cf83
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drivers: fix mask generation when using cond
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2015-01-16 23:50:33 +01:00 |
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Florent Kermarrec
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8f14f67ea6
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simplify UART2Wishbone and add timeout
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2015-01-14 18:10:37 +01:00 |
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Florent Kermarrec
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54597f1bfc
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use new submodules/specials/clock_domains automatic collection
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2015-01-14 13:55:18 +01:00 |
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Florent Kermarrec
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834e9b99be
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host/drivers: add possibility to pass cond dict to ease trigger pattern generation
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2014-12-23 20:53:05 +01:00 |
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Florent Kermarrec
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9bb7e6d0ab
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ethmac: improve testbenchs
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2014-12-21 17:37:25 +08:00 |
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Florent Kermarrec
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ceb675c3f1
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fix cf92821 merge issue
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2014-12-19 21:49:49 +08:00 |
Sebastien Bourdeauducq
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aac34f011f
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gensoc: support user-defined CSR regions
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2014-11-30 22:29:26 +08:00 |
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Sebastien Bourdeauducq
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8ae3a00a94
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gensoc: simplify WB address decoding
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2014-11-30 22:05:51 +08:00 |
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Sebastien Bourdeauducq
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4189440eef
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minicon: small simplifications
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2014-11-28 08:28:39 +08:00 |
Yann Sionneau
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edb1622668
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spiflash: BB write support
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2014-11-27 23:10:39 +08:00 |
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Sebastien Bourdeauducq
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bab6bb7c4a
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gensoc: fix align
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2014-11-27 23:05:36 +08:00 |
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Sebastien Bourdeauducq
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2cd80990e4
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minicon: fix use of phy phases
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2014-11-27 22:13:17 +08:00 |
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Sebastien Bourdeauducq
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8418ccafdc
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minicon: remove unused signals and fix indent
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2014-11-27 22:12:05 +08:00 |
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Yann Sionneau
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cf92821fcf
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Refactor directory hierarchy of sdram phys and controllers
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2014-11-27 22:09:10 +08:00 |
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Yann Sionneau
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f33b285af1
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Minicon: small SDRAM controller
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2014-11-27 22:09:03 +08:00 |
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Florent Kermarrec
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5202f89db1
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ethmac/last_be: remove fake signal (fixed in Migen)
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2014-11-21 14:48:17 -08:00 |
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Sebastien Bourdeauducq
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b7028848b2
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ethmac: use new EndpointDescription API
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2014-11-20 22:32:32 -08:00 |
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Sebastien Bourdeauducq
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33530e0921
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ethmac: style/renaming
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2014-11-20 18:01:48 -08:00 |
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Sebastien Bourdeauducq
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7eaa5f7372
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targets/kc705: avoid ddrphy/ethphy address conflict
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2014-11-20 17:11:57 -08:00 |
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Florent Kermarec
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603c2641bb
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new Ethernet MAC
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2014-11-20 16:47:22 -08:00 |
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Sebastien Bourdeauducq
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f4d6ac8393
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README: remove compiler-rt download instructions
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2014-11-06 18:02:02 -08:00 |
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Sebastien Bourdeauducq
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09773df186
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software: make compiler-rt a submodule
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2014-11-06 18:00:28 -08:00 |
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Florent Kermarrec
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8c5c32751e
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add input pipe stage option
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2014-10-28 20:53:26 +01:00 |
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Florent Kermarrec
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8e4b89849c
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use new direct access on endpoints
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2014-10-20 23:13:37 +08:00 |
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Florent Kermarrec
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34ed315a48
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remove trailing whitespaces
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2014-10-17 17:14:40 +08:00 |
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Florent Kermarrec
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d860813dec
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use new direct access on endpoints
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2014-10-16 17:57:30 +02:00 |
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Florent Kermarrec
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9649b1497c
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uart2wishbone: fix missing payload.d
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2014-10-16 09:37:43 +02:00 |
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Florent Kermarrec
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2319ee0ab7
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uart2wishbone: always use payload.d and not .d
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2014-10-15 12:13:22 +02:00 |
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Florent Kermarrec
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027ddc65ca
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fill __init__.py to simplify imports
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2014-10-10 17:24:36 +02:00 |
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Florent Kermarrec
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bf95ea6c1c
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mila: simplify usage
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2014-10-10 16:17:12 +02:00 |