Florent Kermarrec
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df0ba1b03c
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litescope: create example_designs directory
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2015-02-28 10:42:12 +01:00 |
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Florent Kermarrec
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c4ebf244a1
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litescope: move files and modify import to misoclib.tools.litescope
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2015-02-28 10:33:46 +01:00 |
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Florent Kermarrec
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b274e948dc
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merge litescope
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2015-02-28 10:24:49 +01:00 |
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Florent Kermarrec
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a43c555ee3
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misoclib/com: add spi (only SPIMaster for now)
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2015-02-28 09:43:03 +01:00 |
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Florent Kermarrec
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2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |
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Florent Kermarrec
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6b93849a08
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gensoc: parameter check is now more restrictive, add additional info to help user
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2015-02-28 03:12:00 +01:00 |
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Florent Kermarrec
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8e04ef7b95
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test minicon with de0nano (OK) and fix missing self in gensoc
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2015-02-27 20:00:16 +01:00 |
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Florent Kermarrec
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f1200d6388
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gensoc: move I/O for rom initialization to make.py
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2015-02-27 19:48:07 +01:00 |
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Florent Kermarrec
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074f576340
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targets: add de0nano (100MHz, integrated bios and SDRAM)
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2015-02-27 19:47:32 +01:00 |
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Florent Kermarrec
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cb38580400
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make.py fix indent
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2015-02-27 18:58:36 +01:00 |
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Florent Kermarrec
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5e2e9338d2
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bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
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2015-02-27 17:22:44 +01:00 |
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Florent Kermarrec
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b031c5edae
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targets: fix MiniSoC
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2015-02-27 17:12:37 +01:00 |
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Florent Kermarrec
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e07e124118
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sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir
We will maybe move things, but at least it's in MiSoC now
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2015-02-27 17:07:44 +01:00 |
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Florent Kermarrec
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07b9cabd0d
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gensoc: make it more generic (a SoC does not necessarily have a CPU)
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2015-02-27 16:39:00 +01:00 |
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Florent Kermarrec
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367db268ad
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reserve csr_map 0-->16 for gensoc internal csrs
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2015-02-27 14:18:13 +01:00 |
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Florent Kermarrec
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be0eb8d265
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use cachesize reported in wishbone2lasmi
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2015-02-27 14:13:38 +01:00 |
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Florent Kermarrec
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9814001c79
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create cpu dir and move lm32/mor1kx in it
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2015-02-27 10:51:03 +01:00 |
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Florent Kermarrec
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9f636f7985
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move memtest to sdram
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2015-02-27 10:47:54 +01:00 |
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Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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e4de5a0c9d
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make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
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2015-02-27 10:23:17 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
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Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
Robert Jordens
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2b12679ef6
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add pipistrello target
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2015-02-26 21:35:42 -07:00 |
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Robert Jordens
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c9ed38dec8
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gensoc: missing self.
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2015-02-26 21:32:11 -07:00 |
Sebastien Bourdeauducq
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a3909bb5e2
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-02-26 21:28:12 -07:00 |
Yann Sionneau
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8364fe6674
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target/kc705: allow access to pll_sys signal before BUFG
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2015-02-26 15:56:10 -07:00 |
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Florent Kermarrec
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09fbbca53e
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gensoc: cpus now directly add their verilog sources
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2015-02-26 20:49:21 +01:00 |
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Florent Kermarrec
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5e8a0c496d
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gensoc: add mem_map and mem_decoder to avoid duplications
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2015-02-26 20:12:27 +01:00 |
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Florent Kermarrec
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5ac5ffe359
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gensoc: get platform_id from platform
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2015-02-26 19:07:19 +01:00 |
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Florent Kermarrec
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554731ae44
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targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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2015-02-26 13:08:15 +01:00 |
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Florent Kermarrec
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02b3f51382
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liteeth: fix example_designs generation
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2015-02-26 10:23:38 +01:00 |
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Florent Kermarrec
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00862a383c
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liteeth: fix import (from liteeth --> from misoclib.liteeth)
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2015-02-26 09:48:37 +01:00 |
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Florent Kermarrec
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60effe1d95
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move files to liteeeth and create example_designs directory
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2015-02-26 09:35:14 +01:00 |
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Sebastien Bourdeauducq
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0267868cbe
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remove litex submodule
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2015-02-25 10:40:44 -07:00 |
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Sebastien Bourdeauducq
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658cb0e405
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merge liteeth
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2015-02-25 10:35:39 -07:00 |
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Sebastien Bourdeauducq
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8015d12692
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move files for misoc integration
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2015-02-25 10:34:11 -07:00 |
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Florent Kermarrec
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eef679b6d4
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phy/sim: generate sop/eop
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2015-02-25 17:47:44 +01:00 |
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Florent Kermarrec
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a559fc77c8
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remove upload optimization (we will use wishbone later for performance)
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2015-02-24 18:01:04 +01:00 |
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Florent Kermarrec
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6b7026f521
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add sim phy
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2015-02-24 01:42:56 +01:00 |
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Florent Kermarrec
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b6ebcece95
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add read grouping to etherbone, we now have interesting upload speeds... :)
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2015-02-23 18:58:31 +01:00 |
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Florent Kermarrec
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ac5b7c073a
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test: add make.py to replace static config.py file
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2015-02-23 18:55:19 +01:00 |
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Florent Kermarrec
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71f3a5bf13
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prepare reads grouping to speed up upload
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2015-02-23 18:11:08 +01:00 |
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Florent Kermarrec
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e309ba55ea
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use new Migen sel signal to change the way we upload data (will enable fifo bursts)
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2015-02-23 12:34:04 +01:00 |
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Florent Kermarrec
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d3486dba91
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rle: increase dw automatically when needed
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2015-02-23 09:41:18 +01:00 |
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Florent Kermarrec
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2a2c3af380
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host/dump: optimize get_bits / decode_rle since we can now have large dumps
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2015-02-23 02:14:20 +01:00 |
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Florent Kermarrec
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861c54760e
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host/driver/reg: use burst mode to speed up upload of data (useful with Etherbone)
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2015-02-23 00:49:59 +01:00 |
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Florent Kermarrec
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282c9b9426
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test: add make.py to replace static config.py file
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2015-02-23 00:21:12 +01:00 |
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Florent Kermarrec
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b1dee774cd
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tty working
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2015-02-22 15:23:55 +01:00 |
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Florent Kermarrec
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2fa28c1b5d
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mac: add padding
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2015-02-22 13:56:06 +01:00 |
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Florent Kermarrec
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a802a5c535
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remove MiSoC dependency
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2015-02-21 23:50:25 +01:00 |