8c0982a1d5
Merge pull request #118 from mithro/uart-sync
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uart: Enable buffering the FIFO.
2018-10-28 08:02:22 +01:00
ba0dd5728e
uart: Enable buffering the FIFO.
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On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
2018-10-27 16:04:58 -07:00
f916705313
README: improve instructions for litex_sim
2018-10-27 11:06:53 +02:00
e3935b481e
build/sim/verilator: don't use THEADS parameters when threads=1
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Allow using old (non multi-threaded) version of Verilator
2018-10-27 11:06:34 +02:00
a44181e716
soc_sdram: update litedram
2018-10-19 18:37:55 +02:00
ab6a530a24
bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode
2018-10-18 13:42:51 +02:00
b8be9545cc
build/xilinx/vivado: enable xpm libraries
2018-10-18 09:25:34 +02:00
ab8cf3e345
soc/cores/clock: add margin parameter to create_clkout (default = 1%)
2018-10-16 14:57:37 +02:00
915c2f417a
bios/sdram: improve write/read leveling
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write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
2018-10-10 10:42:56 +02:00
deffa60324
platforms/kc705: add ddram_dual_rank
2018-10-09 15:39:03 +02:00
10624c26da
bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r)
2018-10-09 10:06:51 +02:00
9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart
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sim: serial: Send '\r\n' instead of just '\n'
2018-10-09 07:32:31 +02:00
8877dba7e9
sim: serial: Send '\r\n' instead of just '\n'
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This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART. Since the verilator adapter
is just sending \n commands cannot be executed.
Also, one minor whitespace cleanup. (could remove if needed)
2018-10-09 11:18:11 +09:00
d187921500
cpu_interface: fix select_triple when only one specified
2018-10-08 17:01:04 +02:00
3b27d2ae89
soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains
2018-10-06 21:32:38 +02:00
168b07b9a2
soc_core: add csr range check
2018-10-06 20:55:16 +02:00
ace976242e
build.xilinx: Convert attributes to something Yosys understands.
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Convert keep, dont_touch and async_reg to something Yosys understands.
Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647
2018-10-05 12:48:30 -07:00
6febb6826c
Merge pull request #112 from cr1901/8k-b-evn
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build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-04 21:12:33 +02:00
9cf4ffb3f4
Merge pull request #113 from stffrdhrn/litex-trivial
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Litex trivial
2018-10-04 16:25:11 +02:00
ff6de429f0
Fix help for or1k builds
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The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx. Fix the message to properly represent what
needs to be passed to the commandline.
2018-10-04 23:09:49 +09:00
dafdb8df72
Fix compiler warnings from GCC 8.1
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Fix these 2 warnings:
litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
[-Wstringop-truncation]
strncpy(last_err, s, ERR_MAX_SIZE);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function 'set_last_error',
litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
static char emerg_getc()
2018-10-04 23:07:48 +09:00
2be5205463
build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)
2018-10-04 08:17:44 +02:00
78414c0588
xilinx/viviado: Allow yosys for synthesis.
2018-10-03 21:58:03 -07:00
d13ac3b3d5
cpu/mor1kx: Adding verilog include directory.
2018-10-03 21:57:24 -07:00
9a44f08a3e
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-03 20:53:33 -04:00
dc7cd75757
build.xilinx: Run `phys_opt_design` and generate timing report.
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Makes the flow more similar to migen.
2018-10-03 16:02:43 -07:00
948527b0fe
cores/cpu: revert vexriscv (it seems there is a regression in last version)
2018-10-02 12:30:11 +02:00
15bca4535f
targets/sim: fix integrated_main_ram_size when with_sdram
2018-10-02 11:31:08 +02:00
6e327cda26
bios/sdram: rewrite write_leveling (simplify and improve robustness)
2018-10-01 15:38:19 +02:00
975be6686f
platforms/genesys2: add eth clock timing constraint
2018-10-01 15:37:34 +02:00
934a5da559
soc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-28 13:02:10 +02:00
9097573e71
Merge pull request #109 from cr1901/xip-improve
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Improve XIP Support
2018-09-25 15:32:04 +02:00
082b03016c
targets: use new clock abstraction on all 7-series targets
2018-09-25 09:31:30 +02:00
74e74dc0e7
soc/cores/clock: different clkin_freq_range for pll and mmcm
2018-09-25 09:09:47 +02:00
91d8cc2d6a
soc/cores/clock: different vco_freq_range for pll and mmcm
2018-09-25 09:04:38 +02:00
6cd954940c
soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)
2018-09-25 08:36:18 +02:00
912ca3236b
soc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 23:22:59 +02:00
baec87f530
soc/cores/clock: add S7MMCM support
2018-09-24 23:20:12 +02:00
ef40524924
soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest)
2018-09-24 22:58:23 +02:00
5415b521be
targets/arty: use new clock abstraction module (compile, untested on board)
2018-09-24 22:49:30 +02:00
63fc395006
soc/cores: init clock abstraction module
2018-09-24 22:49:01 +02:00
0ff6d58605
Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section).
2018-09-24 14:48:54 -04:00
8106008184
integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM.
2018-09-24 12:28:45 -04:00
db90619067
integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX).
2018-09-24 11:04:57 -04:00
70a32ed86f
sim/verilator: add multithread support (default=1)
2018-09-24 12:43:29 +02:00
7f0d116d88
soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now)
2018-09-24 10:59:32 +02:00
22febe9582
boards/targets: uniformize things between targets
2018-09-24 10:58:10 +02:00
01b025aafd
soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication
2018-09-24 08:01:32 +02:00
b528a005a0
cores/cpu: add software informations to cpu and simplify cpu_interface
2018-09-24 07:51:41 +02:00
2d785cb0ac
boards/plarforms: fix issues found while testing simple design on all platforms
2018-09-24 02:03:30 +02:00
enjoy-digital
Tim 'mithro' Ansell
Stafford Horne
William D. Jones