1f3c941a78
platforms/m1: move generic platform commands to do_finalize
2013-07-04 19:22:59 +02:00
7e4552bbfc
lx9_microboard: improve compat with other boards
2013-06-27 19:30:57 +02:00
c1cf37f05a
add Avnet Spartan6 LX9 Micrboard platform
2013-06-27 19:18:47 +02:00
e233c62d27
* generic_platform.py: add a finalize() method
...
... to add e.g. timing constraints after the other modules have
had their say and when the signal names are known
2013-06-27 19:17:02 +02:00
6b56428a21
Shorter multipin signal definition
2013-06-25 22:57:31 +02:00
953e603915
xilinx_ise: improve parameter passing
2013-06-01 17:22:57 +02:00
548f2685bb
platform/rhino: rename ismm data out signal to locked
2013-05-30 11:06:02 +02:00
759858f739
Use migen.fhdl.std
2013-05-26 18:07:26 +02:00
e272e68fac
platforms/papilio_pro: swap tx/rx to be consistent with M1
2013-05-19 20:24:47 +02:00
fe64ade1ac
platforms/m1: add pots pins
2013-05-13 15:38:20 +02:00
7a2f31b2e8
platforms/papilio_pro: no reset signal by default
2013-05-07 19:10:18 +02:00
439f032921
crg: support for resetless system clock domain
2013-05-07 19:09:56 +02:00
6a4c194aab
platforms: add KC705
2013-05-07 10:31:12 +02:00
3d0894465c
mibuild: Add platform for Xilinx ML605 board
2013-05-06 14:21:56 +02:00
e4b0e8ed6d
xilinx_ise: enable register balancing
2013-05-06 14:21:39 +02:00
85e06cc100
xilinx_ise: implement NoRetiming synthesis constraint
2013-04-25 14:57:45 +02:00
29eaf068f3
xilinx_ise: do not attempt to source settings file on Windows
2013-04-16 22:55:24 +02:00
31b1960188
xilinx_ise: add --no-source option to disable sourcing of ISE settings file
2013-04-16 22:39:35 +02:00
59d64e92e8
mibuild: define memory card pins of the Milkymist One platorm
...
This patch adds the memory card pins to the M1 platform definition in
mibuild.
I've tentatively named them "mmc". As far as I can tell, "MMC" is not
trademarked ("MultiMediaCard" the new "eMMC" would be), and "MMC" is
commonly used in the industry in a descriptive way to refer to this
sort of interface.
The original Verilog-based M1 calls the interface "mc", but since
several names have changed between milkymist and -ng, I thought I'd
use a more familiar name.
Usage example (clock signal divided by powers of two on the MMC TPs):
https://github.com/wpwrak/ming-ddc-debug/blob/counter-on-mmc/build.py
- Werner
2013-04-12 09:51:57 +02:00
843f8a5bfc
platforms: add Papilio Pro
2013-04-08 20:28:23 +02:00
715d332c3d
crg: apply constraint to IO pins, not internal signals
2013-04-08 20:28:11 +02:00
8cf7c96a53
crg: use new platform.request
2013-03-26 23:08:35 +01:00
38e92eb92b
altera_quartus: fix clock domain name
2013-03-26 23:05:46 +01:00
3b19dfc412
Support for platform info
2013-03-26 19:17:35 +01:00
74cc4d22cd
generic_platform: remove obj in request + add lookup_request
2013-03-26 17:56:53 +01:00
003f1950cd
xilinx_ise: fix clock domain names
2013-03-23 19:37:16 +01:00
797411c1a9
generic_platform: do not create clock domains during Verilog conversion
2013-03-18 18:44:58 +01:00
4bf3190244
MultiReg: remove idomain
2013-03-15 19:54:25 +01:00
6feb6e60b0
New clock_domain API
2013-03-15 18:46:11 +01:00
001beadb97
altera_quartus, de0nano: add copyright notices
2013-03-15 12:37:25 +01:00
f9e07b92a4
Added platform file for DE0 Nano (by Florent Kermarrec)
2013-03-15 11:41:38 +01:00
86d6f1d011
Added support for Altera Quartus (by Florent Kermarrec)
2013-03-15 11:32:12 +01:00
71c8172836
xilinx_ise/CRG_SE: reset inversion support
2013-03-15 11:31:36 +01:00
37d8029848
CRG: support reset inversion
2013-03-15 10:49:18 +01:00
24910173b7
CRG: use new Module API
2013-03-15 10:48:43 +01:00
c06a821452
generic_platform: implicit get_fragment
2013-03-12 16:14:13 +01:00
4d4d6c1f88
platforms/m1: add video mixer extension board
2013-03-05 23:03:01 +01:00
6a412f796e
xilinx_ise: add lock cycle to bitgen
2013-03-01 11:29:40 +01:00
2b902fdcbd
xilinx_ise: import Instance
2013-02-24 15:36:56 +01:00
d60ab1d215
Use new 'specials' API
2013-02-24 12:21:01 +01:00
56ae0f0714
xilinx_ise: disable SRL extraction on synchronizers
2013-02-23 19:43:12 +01:00
ef833422c7
generic_platform/get_verilog: pass additional args to verilog.convert
2013-02-23 19:42:29 +01:00
0321513726
corelogic -> genlib
2013-02-23 19:37:27 +01:00
44ae20d3c4
generic_platform: prefix subsignals
2013-02-20 18:27:04 +01:00
38c3566717
generic_platform: add name
2013-02-14 20:02:35 +01:00
ed4d65f2be
generic_platform: fix IO signal set when using existing record objects
2013-02-13 23:29:33 +01:00
feec035cc8
generic_platform: get absolute path for added sources
2013-02-12 19:16:00 +01:00
709845e618
generic_platform: fix request
2013-02-11 17:54:01 +01:00
ce6701c6e4
platforms/m1: norflash_reset -> norflash_rst_n
2013-02-11 17:46:27 +01:00
4b78d90aad
platforms/m1: add serial pins
2013-02-11 17:46:03 +01:00
f13ad035e1
Support for command line arguments
2013-02-08 22:23:58 +01:00
b092237fa6
xilinx_ise: support building files without running ISE
2013-02-08 20:31:45 +01:00
7b8e8a19f3
Support adding Verilog/VHDL files
2013-02-08 20:25:20 +01:00
32dcfc6d02
generic_platform: support name remapping
2013-02-08 18:27:46 +01:00
9ecfdeccec
platforms/rhino: add PCA9555 I2C expander
2013-02-08 17:44:13 +01:00
fef9d0fc78
generic_platform: fix typo
2013-02-08 17:43:04 +01:00
78f8ec1a53
platforms: add M1
2013-02-08 17:42:35 +01:00
25882c6c83
platforms: ROACH (incomplete)
2013-02-07 22:38:33 +01:00
fb5130fc1f
Initial version
2013-02-07 22:07:30 +01:00
Sebastien Bourdeauducq
Robert Jordens
Florent Kermarrec
Brandon Hamilton
Werner Almesberger