Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
9,924 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

9924 Commits

Author SHA1 Message Date
Matthias Breithaupt e91d4d1a39 Add efinix SEU interface 
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-11-26 08:24:30 +01:00
enjoy-digital 10dcc73676
Merge pull request #2125 from trabucayre/ecp5_diamond_tristate 
build/lattice/common.py: added Tristate support for ECP5 when build with diamond
 2024-11-18 12:40:24 +01:00
Florent Kermarrec 52148c7aad soc/integration/soc_core: Fix with_uartbone changes. 2024-11-18 11:07:51 +01:00
Gwenhael Goavec-Merou 211ce59df4 build/lattice/common.py: added Tristate support for ECP5 when build with diamond 2024-11-17 11:32:33 +01:00
enjoy-digital 8041969e00
Merge pull request #2100 from VOGL-electronic/efinix_io_optimize 
efinix: gpio: use constant output option
 2024-11-15 09:38:50 +01:00
enjoy-digital 8399c919bd
Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream 
feat: add uart_with_dynamic_baudrate to SoCCore
 2024-11-15 09:36:20 +01:00
enjoy-digital 2b3fd723a2
Merge pull request #2101 from VOGL-electronic/bios_spi_fix 
bios: litespi: clear rx queue after write Beta
 2024-11-13 11:12:51 +01:00
enjoy-digital 0f45ea221e
Merge pull request #2119 from long-pham/pr_useAllCPUCores 
Utilizing all available CPU cores in the software make cmd
 2024-11-12 21:45:07 +01:00
enjoy-digital e9e0140c74
Merge pull request #2118 from long-pham/pr_openfpgaloader 
Add FTDI serial number option to openfpgaloader
 2024-11-12 21:40:57 +01:00
enjoy-digital 8ece14849a
Merge pull request #2117 from long-pham/main 
Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl
 2024-11-12 21:40:25 +01:00
enjoy-digital d7a8743f20
Merge pull request #2123 from trabucayre/vhd2vconverter_libraries 
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
 2024-11-12 21:38:38 +01:00
enjoy-digital f056f37c29
Merge pull request #2120 from juiceRv/fix/veril-fst-trace 
Fixes: Fix not close trace file when the sim is finished
 2024-11-12 21:37:09 +01:00
Gwenhael Goavec-Merou f731b36c9b build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL. 2024-11-09 07:55:18 +01:00
Jamey Hicks f53178d712 feat: add uart_with_dynamic_baudrate to SoCCore 2024-11-08 18:49:01 -05:00
Li.XiongHui 5fa144ec3a Fixes: Fix no close trace file when the sim is finished 2024-11-07 14:41:26 +08:00
Long Pham 9cc8bf9866
Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control 2024-11-06 13:48:56 -08:00
enjoy-digital 8b4949edcd
Merge pull request #2115 from CKeilbar/soc-region-check-fix 
Fix SOC region range check
 2024-11-06 22:29:05 +01:00
Florent Kermarrec de9d3ab314 soc/cores/cpu/urv: Add DataBusToWishbone and use it. 2024-11-06 21:59:11 +01:00
Florent Kermarrec 2b3913982c soc/cores/cpu/urv: Add InstructionBusToWishbone and use it. 2024-11-06 21:49:39 +01:00
Long Pham d8e168a81f
Enhance software build performance by utilizing all available CPU cores in the builder 2024-11-06 11:35:28 -08:00
Long Pham 935326e66c
Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD 2024-11-06 11:25:54 -08:00
Florent Kermarrec 1204cfda9d soc/cores/cpu/urv: Fix add_sources. 2024-11-05 17:33:32 +01:00
Florent Kermarrec 20b0e98fe0 cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working. 2024-11-05 17:19:13 +01:00
Chris Keilbart e9613499ea Fix SOC region range check 2024-11-04 12:01:29 -08:00
Florent Kermarrec 0170462fe8 soc/cores/jtag: Fix/Test p_init/p_INIT workaround. 2024-11-04 14:34:28 +01:00
enjoy-digital 3f3249cdf0
Merge pull request #2113 from trabucayre/toolchain_diamond_sdc 
litex/build/lattice/diamond, platform: allows users to add custom sdc files
 2024-11-04 12:53:48 +01:00
Gwenhael Goavec-Merou 47e8b0273f litex/build/lattice/diamond, platform: allows users to add custom sdc files 2024-11-04 12:42:38 +01:00
Florent Kermarrec 175e63ac4c soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes. 2024-11-04 12:40:39 +01:00
Florent Kermarrec 4368d5a9ed test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed. 2024-10-28 21:51:42 +01:00
Florent Kermarrec 61ab30a739 soc/cores/jtag: Revert p_INIT since not tested. 2024-10-28 20:05:47 +01:00
enjoy-digital 10184ad325
Merge pull request #2097 from trabucayre/build_diamond_addition 
Build diamond addition
 2024-10-28 20:05:01 +01:00
enjoy-digital 23df960859
Merge pull request #2102 from Dolu1990/vexiiriscv-macsg 
Vexiiriscv update
 2024-10-28 20:03:06 +01:00
enjoy-digital dd092863f8
Merge branch 'master' into vexiiriscv-macsg 2024-10-28 20:02:56 +01:00
enjoy-digital 18714dfca3
Merge pull request #2104 from andelf/fix/ws2812-of-1-led 
Fixes #2103: calculate  memory depth for WS2812
 2024-10-28 19:53:25 +01:00
Dolu1990 59fc1caac4
Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi 
vexiiriscv: add options and conditions
 2024-10-25 14:26:02 +02:00
Fin Maaß 773fb34079
vexiiriscv: have opensbi behind a option 
this way opensbi things are only activated,
when a linux variant is used.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-25 13:40:20 +02:00
Andelf 8c7e510473 Fixes #2103: calculate memory depth for WS2812 
See-also: https://github.com/m-labs/migen/pull/295
 2024-10-25 11:48:57 +08:00
Dolu1990 24db36ced5 Merge remote-tracking branch 'origin/master' into wuff 2024-10-24 16:02:52 +02:00
Dolu1990 375940ad7d soc/core/vexiiriscv: add macsg support (dma based ethernet) 2024-10-24 16:00:51 +02:00
Fin Maaß d7bf75a75c
bios: litespi: add newline to debug output 
add newline to debug output

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-24 15:12:12 +02:00
Fin Maaß 63fa4fda85
bios: litespi: clear rx queue after write 
clear rx queue at the end of spiflash_master_write().

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-24 15:10:37 +02:00
Fin Maaß 54973eb9cb
build: efinix: use constant output option 
use constant output option, when the output is a `Constant`

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-23 14:12:30 +02:00
Fin Maaß 2d96e99494
build: io: SDRTristate: move check 
check wraped signals instead of before.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-23 11:18:57 +02:00
Fin Maaß 70f4a349e5
efinix: ifacewriter: fix in output 
fix in OUTPUT

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-23 11:10:16 +02:00
Fin Maaß d6eec8e76d
efinix: ifacewriter: gpio: share common code 
share common code for INPUT, INOUT and OUTPUT.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-10-23 11:08:58 +02:00
enjoy-digital c1225736a8
Merge pull request #2098 from enjoy-digital/urv 
Add initial uRV CPU support.
 2024-10-17 19:45:44 +02:00
Florent Kermarrec 5f463dba87 CHANGES.md: Update. 2024-10-17 17:45:50 +02:00
Florent Kermarrec aab8912f5a soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU. 2024-10-17 17:44:40 +02:00
Florent Kermarrec 9449d25911 soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory. 
- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
 2024-10-17 16:54:20 +02:00
Florent Kermarrec edb56e73aa soc/cores/cpu: Add initial uRV CPU support (not yet working). 2024-10-16 22:24:07 +02:00